You should find out first, if building a whole new processor is necessary
and viable. I have collected quite a number of articles about OO
processors including the Xerox machines, Recursive(both SuperCISC) and
SOAR(RISC). There are also some Java processors around. It seems that the
difficult problems are OO storage and method finding whereas the actual
bytecode-interpreter is a bit more simple. My personal interest faded when
I realized how much work it would be and when I read an article by David
Ungar "Is Hardware Support for OO Languages really necessary". He says no
and he was one of th main designers of SOAR. Language requirements change
and processors are rather static which might lead to dead ends as CS goes
on.

It seems much more viable to use an existing processor and a FPGA for
peripheral support. There exists such a design at the Technical University
in Berlin and I'm triyng to get my hands on such a board. It uses an ARM,
has 32 MB SDRAM and an FPGA for some other stuff. Material costs are about
100EUR. Also the DEC Itsy looks promising as a base design. If you havcan
spend some money have a look at "Fred" at
http://www.kws-computer.de/kwscom/pro86E.html

In my opinion it might be interesting to have two memory buses. One very
fast (at processor rate) running the VM and a slower for the image. There
is an inherent bandwidth preservation in bytecoded languages.

Torsten Sadowski

P.S. The last interim Dynabook was the Newton. Pity it died.

On Wed, 19 Mar 2003, Hannes Hirzel wrote:

> Tim Rowledge <tim at sumeru.stanford.edu> wrote:
> > Gimme money.
> >
> > There are several of us reasonably qualified to do something like this
> > but where is the money going to come from? It's a sizable project that
> > would involve a number of people that would need enough income to
> > survive the experience; sorry but I'm not in a position to subsidize any
> > of this.
> >
> > Once it existed what could we do with it to recoup the costs?  Competing
> > against Intel/Motorola/whoever is not a game for fun - unless you can
> > pay for said fun.
> >
> > tim
> > --
> > Tim Rowledge, tim at sumeru.stanford.edu, http://sumeru.stanford.edu/tim
> > Useful random insult:- One pearl short of a necklace.
>
> As I understand Ned  - his baseline argument is that such a project
> nowadays should be relatively easy to do with standard FPGA parts
> and stuff. It is not about competing. It is just about trying out
> old new ways of doing things and having great fun.
> Just to see what happens. Sharing the x-perience of achievieng
> something what people normally consider to be hard.
>
> If it isn't fun and easy to do we shoudn't do it.
>
> And perhaps there is a hardware champion out there would
> assemble a few boards for the more software oriented types
> to play with. Just a PC board with an ethernet connection
> and a facility to program the FPGA.
>
> -- Hannes
>
>
>