Jecel Assumpcao Jr <jecel at merlintec.com>  wrote...

>Now suppose you can get a competitive solution working on an FPGA. If
>somebody comes up with a better idea, just patch your VHDL and
>recompile! And you get to ride Moore's law like all the big guys since
>faster and cheaper FPGAs will be coming out every year.

I'm sure Jecel knows this but, to those who have just learned what FPGAs are and who are excited about them, the double-whammy is that, once you have one that works, there is a whole industry built around the ability to take just about any FPGA pattern, and "compile" it into *real* gate arrays.  These tend to be much more compact (so you can make even bigger ones), to run 5-20 times faster, and to use less power as well.

The other thing I have to say on this thread is a bit against the flow.  Namely, today's screaming C chips are not all that bad for OOP.  Consider what the best JIT VMs do, and ask yourself how much better you think you can do.  You really have to get specific about what you think is needed and how much time you think it would save.  Given how well a good JIT can do, it may make more sense to put those architectural brain cells to work on the problem of distributing OOP in a manner that many processors can work together.  (Or finishing Jitter 5 ;-).

	- Dan