Dynabook hw cost

Jecel Assumpcao Jr jecel at merlintec.com
Thu May 24 17:12:48 UTC 2007


Tim Rowledge wrote on Tue, 22 May 2007 22:16:13 -0700
> On 22-May-07, at 8:26 PM, Matthew Fulmer wrote:
> > Jecel is the local expert in processors. You should check out
> > his site:
> > http://www.merlintec.com:8080/hardware

Thanks for the "local expert" comment :-)

I am catching up with the past week's email and came across this
interesting discussion. There is a particularly relevant link nearly
hidden at the bottom of the page you indicated which Brad might find
interesting - the list of Smalltalk computers.

> I still think a very simple RISC architecture with a substantial  
> above-the-bus chunk of memory that can be used for 'microcode' or  
> data store,

Your wish is my command - check out my RISC42 core design. Its 16 bit
instruction set was heavily influenced by my effort to come up with a
nice microcode for a Squeak processor.

> no traditional (and expensive) cache,

Caches have their uses as well, specially if they are tweaked to deal
with objects and PICs. I see no reason not to have both caches and
visible local memory so all my recent designs have had this style.

> transputer-like  
> communication channels to other cores

That might be a bit simplistic, and even the last Transputer from Inmos
(T9000) replaced that with hardware routing. Perhaps something more like
the old J-Machine from MIT (a Smalltalk computer with 1024 processors)?

> and probably no special  
> floating point hardware would be nice.

How about bitblt in hardware and stuff like that?

> If you can get to a state  
> where dozens/hundreds of cores can be sensibly used then one or two  
> can spend their time as floating point units and if needed many more  
> can join in. Likewise for video stream processing.

Indeed, which is the spirit of Chuck Moore's current design (24 Forth
processors): http://www.intellasys.net/

And this is also why I decided to register the "Plurion" trademark
(multiple RISC42 cores). For my thesis, however, I will be trying to
take advantage of the fact that the hardware is implemented using a FPGA
to replace one or two processors with hardware implementation of key
objects if the adaptive compilation system (Self/Strongtalk style)
decides these are extreme "hot spots" in the current execution.

The project Matthew mentioned is the one named "RNA" on the above page.
That one doesn't have a memory/processor separation at all.

> The really hard part is getting people to actually think about multi- 
> processing solutions to problems. The software world is far too  
> comfortable with single-thread thinking and the cosy fantasy version  
> of Moore's Law.

That died with the Pentium 4. Nearly half of the recent talks at
http://ee380.stanford.edu/ start out with some graph that proves just
that. The software people are slowing starting to figure this out.

But back to this thread's subject: the XO is not a particularly good
indication of how much a dynabook could cost. It is a great effort to
reduce cost but has far too much PC legacy overhead. Certainly some
laptop that costs around $500 retail could approach $175 when bought
directly off the assembly line in huge quantities and with absolutely no
taxes. Not that this would make it as nice a computer for children as
the XO, of course! But I feel we should aim to have a Dynabook for $30
under these conditions (some $80 retail) by the end of this decade.

-- Jecel



More information about the Squeak-dev mailing list