Eliot Miranda wrote:
>
>
> Superficially this looks good. But it is only a part of the semantics.
> This is a fairly abstract semantics. It leaves out definitions of
> registers (e.g. DEST $B"+(B DEST + SRC + CF;) and all the instruction
> decode, which on x86 is complex and easy to screw up.

if you find anything better, please let me know. I'm still interested in
this.

Appendix B, on the second part of the Instrution Set Reference manual
(http://www.intel.com/products/processor/manuals/). I couldn't find it now,
I'll see if I can find it home, but somewhere I have a Squeak implementation
of a IA-32 decompiler. At that time I based on an old text version of the
table "General Purpose Instruction Formats and Encodings for Non-64-Bit
Modes" in that document. I remember that after some tweaking I could
"compile" the table. This is when I started trying to compile the pseudocode
for instruction, but I never got too far with it.

Another place where to find "compilable" information of how to decode
the instructions is in the header of each instruction on the same manual.
It is a very precise specification, for example:

64-Bit Compat/
Opcode Instruction Mode Leg Mode Description
04 ib ADD AL, imm8 Valid Valid Add imm8 to AL.
05 iw ADD AX, imm16 Valid Valid Add imm16 to AX.
05 id ADD EAX, imm32 Valid Valid Add imm32 to EAX.

01 /r ADD r/m16, r16 Valid Valid Add r16 to r/m16.
01 /r ADD r/m32, r32 Valid Valid Add r32 to r/m32.
02 /r ADD r8, r/m8 Valid Valid Add r/m8 to r8.
ADD r8*, r/m8* Valid N.E. Add r/m8 to r8.

the r/m notation has a very precise meaning and encoding, so does the /r
and r32.
Yes, there are some asterisks, but they are clearly marked. Again, I'm
interested in
any options you find!

richie