On Tue, Mar 17, 2009 at 2:45 PM, Claus Kick <claus_kick at web.de> wrote:

> Eliot Miranda wrote:
> *snip*
>
>>
>> ...and SPARC is one of the worst 64-bit implementations out there.
>>  Question, how much bigger is a 64-bit literal load instruction vs a
>> 32-bit
>> literal load in x86/x86-64 and SPARC32/SPARC64?
>>
>
> Interesting though off topic tidbit, therefore an OT question: is that
> aimed at SPARC as a (for lack of better word) architecture or do you have a
> specific implementation in mind? (*curious*)


I know nothing about SPARC internals and so cannot suggest an
implementation.

Part of my complaint is the name, Scaleable Processor ARCitecture.  The
current SPARC requires 6 (reads it and weep, _6_) 32-bit instructions to
synthesize an arbitrary 64-bit literal.  It hasn't scaled to 64-bits;
consequently there are a range of addressing models in 64-bit SPARC
compilers, 20-something-bits 40-something bits (I forget the details) and
64-bits.  By contrast there are 10-byte instructions that do 64-bit literals
loads in x86-64.  So a 200% overhead vs a 25% overhead.

One can try and use the branch and link instruction to jump over the
literal, grab the pc and indirect through it, but IIRC that's a slow 5 word
sequence that can't be used in leaf routines.  But this is off the top of my
head so don't quote me.

I would have thought that somehow one could define a three word instruction
saying "load the next two words into a register and skip them: or, if the
anachronism of the delay slot must still be respected, a 4 word instruction
saying "load the two words after the following instruction into a register
and skip them, executing the instruction in the delay slot".
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