[squeak-dev] Squeak RISC-V ISA 32I Implementation

Eric Gade eric.gade at gmail.com
Sun Jul 12 19:30:36 UTC 2020

Hi all,

I've hit a small milestone on a personal project that I would like to
share. It is a Squeak implementation of the RISC-V ISA, along with a (very
basic for now) CPU and memory for simulation and testing. You can find the
project here <https://github.com/darth-cheney/safe-bet/>.

So far I have only implemented the basic 32I instructions from the
unprivileged ISA <https://riscv.org/specifications/isa-spec-pdf/>. My goal
is to get the basic extension instructions implemented too, along with the
64I instructions. In terms of personal goals for the project, I'm thinking
of doing something stupid like writing my own OS and Squeak seems like the
kind of reduced-frustration environment that might curtail some of the
inevitable hair-pulling.

Disclaimer: my knowledge of the low-level systems stuff is quite limited,
so writing this package has been a learning experience. That's a polite way
of saying "I have no idea what I'm actually doing." So if you spot any
design choices you think are offensive or downright insane, please do file
an issue or send me a message. I'm hoping that somehow this will be useful
to the community.

If you'd like to give this a whirl, your best bet is to check out
RVCPUBasic >> #bootstrap:, which takes an ordered collection of
RVInstructions and loads them into the simulated memory starting at address
0. You can then send the #start message to the CPU and it will run through
the instructions in memory one by one. For the moment there aren't any
example "programs" to run here -- I'm open to suggestions!

I've tried to write tests as comprehensively as possible, but I'm sure I'm
missing some important cases and there are certainly going to be bugs.

Shout out to the TwosComplement package
<http://www.squeaksource.com/TwosComplement/>, which really helped me
figure things out when I was in a bind.

The repo is called "Safe Bet" because it's a "small(talk) risc"

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