[Vm-dev] VM Maker: VMMaker.oscog-tpr.783.mcz

commits at source.squeak.org commits at source.squeak.org
Fri Jun 27 01:19:47 UTC 2014


tim Rowledge uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-tpr.783.mcz

==================== Summary ====================

Name: VMMaker.oscog-tpr.783
Author: tpr
Time: 26 June 2014, 9:16:55.051 am
UUID: 0799fd6c-82b7-458c-af82-b10f9738a635
Ancestors: VMMaker.oscog-eem.782

correct mistaken callersaved reg stuff
Fix concretizedRetN to not over-bump the SP

=============== Diff against VMMaker.oscog-eem.782 ===============

Item was changed:
  ----- Method: CogARMCompiler>>callerSavedRegisterMask (in category 'accessing') -----
  callerSavedRegisterMask
  	"registers r0-r3, the lowest four, +lr"
+ 		^2r100000000001111!
- 		^16r40F!

Item was changed:
  ----- Method: CogARMCompiler>>concretizeRetN (in category 'generate machine code - concretize') -----
  concretizeRetN
  	"Will get inlined into concretizeAt: switch."
  	<inline: true>
  	| offset |
  	offset := operands at: 0.
  	offset = 0 ifTrue:
  		[self machineCodeAt: 0 put: (self mov: PC rn: LR). "pop	{pc}"
  		^machineCodeSize := 4].
  	self assert: offset < 32. "We have an 8 bit immediate. If needed, we could rotate it less than 30 bit."
+ 
+ 	self machineCodeAt: 0 put: (self add: SP rn: SP imm: offset  ror: 0).
- 	"add sp, sp, #n, ROR (15<<2) <- ie shift left 2 to convert words to bytes"
- 	self machineCodeAt: 0 put: (self add: SP rn: SP imm: offset ror: 30).
  	self machineCodeAt: 4 put: (self mov: PC rn: LR).  "pop	{pc}"
  	^machineCodeSize := 8!

Item was changed:
  ----- Method: CogARMCompiler>>genPushRegisterArgsForAbortMissNumArgs: (in category 'smalltalk calling convention') -----
  genPushRegisterArgsForAbortMissNumArgs: numArgs
  	"Ensure that the register args are pushed before the outer and
  	 inner retpcs at an entry miss for arity <= self numRegArgs.  The
  	 outer retpc is that of a call at a send site.  The inner is the call
  	 from a method or PIC abort/miss to the trampoline."
  
  	"Putting the receiver and args above the return address means the
  	 CoInterpreter has a single machine-code frame format which saves
  	 us a lot of work."
  
  	"Iff there are register args convert
  		sp		->	outerRetpc		(send site retpc)
  		linkReg = innerRetpc		(PIC abort/miss retpc)
  	 to
  		base	->	receiver
  					(arg0)
  					(arg1)
  		sp		->	outerRetpc		(send site retpc)
+ 		linkReg = innerRetpc		(PIC abort/miss retpc) - we will rely upon the next bit of code generation to push the current lr if required"
- 		linkReg = innerRetpc		(PIC abort/miss retpc)"
  	numArgs <= cogit numRegArgs ifTrue:
  		[self assert: cogit numRegArgs <= 2.
  		 cogit MoveMw: 0 r: SPReg R: TempReg. "Save return address"
  		 cogit MoveR: ReceiverResultReg Mw: 0 r: SPReg.
  		 numArgs > 0 ifTrue:
  			[cogit PushR: Arg0Reg.
  			 numArgs > 1 ifTrue:
  				[cogit PushR: Arg1Reg]].
+ 		cogit PushR: TempReg] "push back return address"!
- 		cogit PushR: TempReg] "Restore return address"!



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