[Vm-dev] Re: Float hierarchy for 64-bit Spur
bert at freudenbergs.de
Fri Nov 21 12:47:50 UTC 2014
On 21.11.2014, at 02:51, Eliot Miranda <eliot.miranda at gmail.com> wrote:
> Hi All,
> 64-bit Spur can usefully provide an immediate float, a 61-bit subset of the ieee double precision float. The scheme steals bits from the mantissa to use for the immediate's 3-bit tag pattern. So values have the same precision as ieee doubles, but can only represent the subset with exponents between 10^-38 and 10^38, the single-precision range.
This is worded confusingly. It sounds like the mantissa has 3 bits less, which would make it less precise.
Here is how I understood it: The mantissa is stored with its full 52 bits of precision (*). But only the lower 8 bits of the 11-bit exponent are stored. If the upper 3 bits of the exponent are needed, then a boxed float is created.
I guess I know what you meant, that it is the 3 lowest significant bits in an oop which are used for tagging immediate objects, and in an IEEE double that is part of the mantissa. But these 3 bits are not lost, but moved elsewhere (namely where the 3 highest significant bits of the exponent used to be stored).
Did I understand correctly? You haven't pushed the code yet so I couldn't verify.
- Bert -
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