[Vm-dev] VM Maker: VMMaker.oscog-tpr.1175.mcz
commits at source.squeak.org
commits at source.squeak.org
Wed Apr 8 00:10:15 UTC 2015
tim Rowledge uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-tpr.1175.mcz
==================== Summary ====================
Name: VMMaker.oscog-tpr.1175
Author: tpr
Time: 7 April 2015, 5:08:52.952 pm
UUID: 2d20a320-fb8d-4b8f-9086-d24ef877f591
Ancestors: VMMaker.oscog-eem.1174
Add the Stop & PushCq abstract instructions support for ARM.
Add some more quick-constant processing, just because.
=============== Diff against VMMaker.oscog-eem.1174 ===============
Item was changed:
----- Method: CogARMCompiler>>computeMaximumSize (in category 'generate machine code') -----
computeMaximumSize
+ "Because we don't use Thumb, each ARM instruction has 4 bytes. Some abstract opcodes need more than one instruction. We only handle those in this caseOf: and let the default return 4"
- "Because we don't use Thumb, each ARM instruction has 4 bytes. Some abstract opcodes need more than one instruction."
(opcode between: FirstShortJump and: LastJump) ifTrue:
[^maxSize := 16].
opcode
caseOf: {
[Label] -> [^maxSize := 0].
[AlignmentNops] -> [^maxSize := (operands at: 0) - 1].
[MoveAwR] -> [^maxSize := (self isAddressRelativeToVarBase: (operands at: 0))
ifTrue: [4]
ifFalse: [20]].
[MoveCqR] -> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 4]
ifFalse: [maxSize := 16]].
[MoveCwR] -> [^maxSize := 16].
[MoveRAw] -> [^maxSize := (self isAddressRelativeToVarBase: (operands at: 1))
ifTrue: [4]
ifFalse: [20]].
[MoveRMwr] -> [self is12BitValue: (operands at: 1)
ifTrue: [ :u :i | ^maxSize := 4]
ifFalse: [ ^maxSize := 20 ]].
[MoveRMbr] -> [self is12BitValue: (operands at: 1)
ifTrue: [ :u :i | ^maxSize := 4]
ifFalse: [ ^maxSize := 20 ]].
[MoveMwrR] -> [self is12BitValue: (operands at: 0)
ifTrue: [ :u :i | ^maxSize := 4]
ifFalse: [ ^maxSize := 20 ]].
[MoveMbrR] -> [self is12BitValue: (operands at: 0)
ifTrue: [ :u :i | ^maxSize := 4]
ifFalse: [ ^maxSize := 20 ]].
[PrefetchAw] -> [^maxSize := (self isAddressRelativeToVarBase: (operands at: 1))
ifTrue: [4]
ifFalse: [20]].
[Call] -> [^maxSize := 20 "recomputed in #sizePCDependentInstruction."].
[RetN] -> [^(operands at: 0) = 0
ifTrue: [maxSize := 4]
ifFalse: [maxSize := 8]].
[CmpCqR] -> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 4]
ifFalse: [maxSize := 20]].
[AddCqR] -> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 4]
ifFalse: [maxSize := 20]].
[BICCqR] -> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 4]
ifFalse: [maxSize := 20]].
[SubCqR] -> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 4]
ifFalse: [maxSize := 20]].
[AndCqR] -> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 4]
ifFalse: [maxSize := 20]].
[AndCqRR] -> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 4]
ifFalse: [maxSize := 20]].
[OrCqR] -> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 4]
ifFalse: [maxSize := 20]].
[TstCqR] -> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 4]
ifFalse: [maxSize := 20]].
[XorCqR] -> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 4]
ifFalse: [maxSize := 20]].
[CmpCwR] -> [^maxSize := 20].
[AddCwR] -> [^maxSize := 20].
[SubCwR] -> [^maxSize := 20].
[AndCwR] -> [^maxSize := 20].
[OrCwR] -> [^maxSize := 20].
[XorCwR] -> [^maxSize := 20].
[JumpR] -> [^maxSize := 4].
[JumpFPEqual] -> [^maxSize := 8].
[JumpFPNotEqual] -> [^maxSize := 8].
[JumpFPLess] -> [^maxSize := 8].
[JumpFPGreaterOrEqual]-> [^maxSize := 8].
[JumpFPGreater] -> [^maxSize := 8].
[JumpFPLessOrEqual] -> [^maxSize := 8].
[JumpFPOrdered] -> [^maxSize := 8].
[JumpFPUnordered] -> [^maxSize := 8].
[JumpLong] -> [^maxSize := 20].
[JumpLongZero] -> [^maxSize := 20].
[JumpLongNonZero] -> [^maxSize := 20].
[LoadEffectiveAddressMwrR]
-> [^self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| maxSize := 4]
ifFalse: [maxSize := 20]].
[PushCw] -> [^maxSize := 20].
+ [PushCq] -> [^self rotateable8bitImmediate: (operands at: 0)
+ ifTrue: [:r :i| maxSize := 8]
+ ifFalse: [maxSize := 20]].
}
otherwise: [^maxSize := 4].
^4 "to keep C compiler quiet"
!
Item was changed:
----- Method: CogARMCompiler>>concretizeMoveCqR (in category 'generate machine code - concretize') -----
concretizeMoveCqR
"Will get inlined into concretizeAt: switch."
"If the quick constant is in fact a shiftable 8bit, generate the apropriate MOV, otherwise do what is necessary for a whole word."
<inline: true>
+ |word reg|
+ word := operands at: 0.
+ reg := self concreteRegister: (operands at: 1).
self
rotateable8bitImmediate: (operands at: 0)
+ ifTrue: [:rot :immediate |
- ifTrue: [:rot :immediate | | reg |
- reg := self concreteRegister: (operands at: 1).
self machineCodeAt: 0 put: (self mov: reg imm: immediate ror: rot).
^machineCodeSize := 4]
+ ifFalse: [|invVal|
+ word <0
+ ifTrue:[invVal := -1 - word]
+ ifFalse:[invVal := word bitInvert32].
+ self rotateable8bitImmediate: invVal
+ ifTrue: [ :rot :immediate |
+ self machineCodeAt: 0 put: (self mvn: ConcreteIPReg imm: immediate ror: rot).
+ ^machineCodeSize := 4]
+ ifFalse: [^self concretizeMoveCwR]]
- ifFalse: [^self concretizeMoveCwR].
!
Item was changed:
----- Method: CogARMCompiler>>concretizeNop (in category 'generate machine code - concretize') -----
concretizeNop
"Will get inlined into concretizeAt: switch."
<inline: true>
+ "(CogARMCompiler new mov: 0 rn: 0 ) hex -> MOV r0, r0"
- "MOV r0, r0"
self machineCodeAt: 0 put: 16rE1A00000.
^machineCodeSize := 4
!
Item was added:
+ ----- Method: CogARMCompiler>>concretizePushCq (in category 'generate machine code - concretize') -----
+ concretizePushCq
+ | word instrOffset |
+ <inline: true>
+ self break.
+ word := operands at: 0.
+ self
+ rotateable8bitImmediate: word
+ ifTrue: [:rot :immediate |
+ self
+ machineCodeAt: 0
+ put: (self
+ mov: ConcreteIPReg
+ imm: immediate
+ ror: rot).
+ instrOffset := 4]
+ ifFalse: [| invVal |
+ word < 0
+ ifTrue: [invVal := -1 - word]
+ ifFalse: [invVal := word bitInvert32].
+ self
+ rotateable8bitImmediate: invVal
+ ifTrue: [:rot :immediate |
+ self
+ machineCodeAt: 0
+ put: (self
+ mvn: ConcreteIPReg
+ imm: immediate
+ ror: rot).
+ instrOffset := 4]
+ ifFalse: [instrOffset := self
+ at: 0
+ moveCw: word
+ intoR: ConcreteIPReg]].
+ self
+ machineCodeAt: instrOffset
+ put: (self pushR: ConcreteIPReg).
+ ^ machineCodeSize := instrOffset + 4!
Item was added:
+ ----- Method: CogARMCompiler>>concretizeStop (in category 'generate machine code - concretize') -----
+ concretizeStop
+ "generate a BKPT instruction. We could, given a good enough creative impulse and an over-active sense of humour, add some numerically encoded witticism to this instruction in bits 8-19 & 0-3. It has no effect on the execution but can be a way to specify which breakpoint has been hit etc."
+ <inline: true>
+ machineCode at: 0 put: (AL <<28 bitOr: (16r42 <<20 bitOr:(7<<4))).
+ ^machineCodeSize := 4!
Item was changed:
----- Method: CogARMCompiler>>dispatchConcretize (in category 'generate machine code') -----
dispatchConcretize
"Attempt to generate concrete machine code for the instruction at address.
This is the inner dispatch of concretizeAt: actualAddress which exists only
to get around the branch size limits in the SqueakV3 (blue book derived)
bytecode set."
<returnTypeC: #void>
cond ifNotNil:
[self concretizeConditionalInstruction.
^self].
opcode caseOf: {
"Noops & Pseudo Ops"
[Label] -> [^self concretizeLabel].
[AlignmentNops] -> [^self concretizeAlignmentNops].
[Fill16] -> [^self concretizeFill16].
[Fill32] -> [^self concretizeFill32].
[FillFromWord] -> [^self concretizeFillFromWord].
[Nop] -> [^self concretizeNop].
"Control"
[Call] -> [^self concretizeCall].
[JumpR] -> [^self concretizeJumpR].
[JumpLong] -> [^self concretizeConditionalJumpLong: AL].
[JumpLongZero] -> [^self concretizeConditionalJumpLong: EQ].
[JumpLongNonZero] -> [^self concretizeConditionalJumpLong: NE].
[Jump] -> [^self concretizeConditionalJump: AL].
[JumpZero] -> [^self concretizeConditionalJump: EQ].
[JumpNonZero] -> [^self concretizeConditionalJump: NE].
[JumpNegative] -> [^self concretizeConditionalJump: MI].
[JumpNonNegative] -> [^self concretizeConditionalJump: PL].
[JumpOverflow] -> [^self concretizeConditionalJump: VS].
[JumpNoOverflow] -> [^self concretizeConditionalJump: VC].
[JumpCarry] -> [^self concretizeConditionalJump: CS].
[JumpNoCarry] -> [^self concretizeConditionalJump: CC].
[JumpLess] -> [^self concretizeConditionalJump: LT].
[JumpGreaterOrEqual] -> [^self concretizeConditionalJump: GE].
[JumpGreater] -> [^self concretizeConditionalJump: GT].
[JumpLessOrEqual] -> [^self concretizeConditionalJump: LE].
[JumpBelow] -> [^self concretizeConditionalJump: CC]. "unsigned lower"
[JumpAboveOrEqual] -> [^self concretizeConditionalJump: CS]. "unsigned greater or equal"
[JumpAbove] -> [^self concretizeConditionalJump: HI].
[JumpBelowOrEqual] -> [^self concretizeConditionalJump: LS].
[JumpFPEqual] -> [^self concretizeFPConditionalJump: EQ].
[JumpFPNotEqual] -> [^self concretizeFPConditionalJump: NE].
"[JumpFPLess] -> [^self concretizeFPConditionalJump: LT].
[JumpFPGreaterOrEqual] -> [^self concretizeFPConditionalJump: GE].
[JumpFPGreater] -> [^self concretizeFPConditionalJump: GT].
[JumpFPLessOrEqual] -> [^self concretizeFPConditionalJump: LE].
[JumpFPOrdered] -> [^self concretizeFPConditionalJump: VC].
[JumpFPUnordered] -> [^self concretizeFPConditionalJump: VS]."
[RetN] -> [^self concretizeRetN].
"Arithmetic"
[AddCqR] -> [^self concretizeAddCqR].
[AddCwR] -> [^self concretizeDataOperationCwR: AddOpcode].
[AddRR] -> [^self concretizeDataOperationRR: AddOpcode].
"[AddRdRd] -> [^self concretizeSEE2OpRdRd: 16r58]."
[AndCqR] -> [^self concretizeAndCqR].
[AndCqRR] -> [^self concretizeAndCqRR].
[AndCwR] -> [^self concretizeDataOperationCwR: AndOpcode].
[AndRR] -> [^self concretizeDataOperationRR: AndOpcode].
[BICCqR] -> [^self concretizeDataOperationCqR: BicOpcode].
[CmpCqR] -> [^self concretizeDataOperationCqR: CmpOpcode].
[CmpCwR] -> [^self concretizeDataOperationCwR: CmpOpcode].
[CmpRR] -> [^self concretizeDataOperationRR: CmpOpcode].
[CmpRdRd] -> [^self concretizeCmpRdRd].
"[DivRdRd] -> [^self concretizeSEE2OpRdRd: 16r5E].
[MulRdRd] -> [^self concretizeSEE2OpRdRd: 16r59]."
[OrCqR] -> [^self concretizeDataOperationCqR: OrOpcode].
[OrCwR] -> [^self concretizeDataOperationCwR: OrOpcode].
[OrRR] -> [^self concretizeDataOperationRR: OrOpcode].
[SubCqR] -> [^self concretizeSubCqR].
[SubCwR] -> [^self concretizeDataOperationCwR: SubOpcode].
[SubRR] -> [^self concretizeDataOperationRR: SubOpcode].
"[SubRdRd] -> [^self concretizeSEE2OpRdRd: 16r5C]."
[SqrtRd] -> [^self concretizeSqrtRd].
[TstCqR] -> [^self concretizeTstCqR].
[XorCqR] -> [^self concretizeDataOperationCqR: XorOpcode].
[XorCwR] -> [^self concretizeDataOperationCwR: XorOpcode].
[XorRR] -> [^self concretizeDataOperationRR: XorOpcode].
[NegateR] -> [^self concretizeNegateR].
[LoadEffectiveAddressMwrR] -> [^self concretizeLoadEffectiveAddressMwrR].
[ArithmeticShiftRightCqR] -> [^self concretizeArithmeticShiftRightCqR].
[LogicalShiftRightCqR] -> [^self concretizeLogicalShiftRightCqR].
[LogicalShiftLeftCqR] -> [^self concretizeLogicalShiftLeftCqR].
[ArithmeticShiftRightRR] -> [^self concretizeArithmeticShiftRightRR].
[LogicalShiftLeftRR] -> [^self concretizeLogicalShiftLeftRR].
[LogicalShiftRightRR] -> [^self concretizeLogicalShiftRightRR].
"Data Movement"
[MoveCqR] -> [^self concretizeMoveCqR].
[MoveCwR] -> [^self concretizeMoveCwR].
[MoveRR] -> [^self concretizeMoveRR].
[MoveAwR] -> [^self concretizeMoveAwR].
[MoveRAw] -> [^self concretizeMoveRAw].
"While the two MoveMbR and MoveMwR are quite similar (off by 1 bit), they differ way more to
MoveM16R and MoveM64R. Because of that, they are not merged."
[MoveMbrR] -> [^self concretizeMoveMbrR].
[MoveRMbr] -> [^self concretizeMoveRMbr].
[MoveM16rR] -> [^self concretizeMoveM16rR].
[MoveM64rRd] -> [^self concretizeMoveM64rRd].
[MoveMwrR] -> [^self concretizeMoveMwrR].
[MoveXbrRR] -> [^self concretizeMoveXbrRR].
[MoveRXbrR] -> [^self concretizeMoveRXbrR].
[MoveXwrRR] -> [^self concretizeMoveXwrRR].
[MoveRXwrR] -> [^self concretizeMoveRXwrR].
[MoveRMwr] -> [^self concretizeMoveRMwr].
[MoveRdM64r] -> [^self concretizeMoveRdM64r].
[PopR] -> [^self concretizePopR].
[PushR] -> [^self concretizePushR].
+ [PushCq] -> [^self concretizePushCq].
[PushCw] -> [^self concretizePushCw].
[PrefetchAw] -> [^self concretizePrefetchAw].
+ [Stop] -> [^self concretizeStop].
"Conversion"
[ConvertRRd] -> [^self concretizeConvertRRd].
"ARM specific opcodes"
[LDMFD] -> [^self concretizeLDMFD].
[STMFD] -> [^self concretizeSTMFD].
[SMULL] -> [^self concretizeSMULL] }!
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