[Vm-dev] VM Maker: VMMaker.oscog-cb.1185.mcz

[commits at source.squeak.org]

ClementBera uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-cb.1185.mcz

==================== Summary ====================

Name: VMMaker.oscog-cb.1185
Author: cb
Time: 13 April 2015, 11:12:19.768 am
UUID: f6bfc799-11a0-4e86-8168-994f0af7fac9
Ancestors: VMMaker.oscog-rmacnak.1184

Improved register allocation.

=============== Diff against VMMaker.oscog-rmacnak.1184 ===============

Item was changed:
  ----- Method: CogAbstractInstruction>>availableRegisterOrNilFor: (in category 'register allocation') -----
  availableRegisterOrNilFor: liveRegsMask
  	"Answer an unused abstract register in the liveRegMask.
  	 Subclasses with more registers can override to answer them."
  	<returnTypeC: #sqInt>
+ 	self flag: 'searching physical registers that are not assigned to abstract registers first will do a better job and allocate with fewer conflicts'.
  	(liveRegsMask anyMask: (cogit registerMaskFor: Arg1Reg)) ifFalse:
  		[^Arg1Reg].
  	(liveRegsMask anyMask: (cogit registerMaskFor: Arg0Reg)) ifFalse:
  		[^Arg0Reg].
  	(liveRegsMask anyMask: (cogit registerMaskFor: SendNumArgsReg)) ifFalse:
  		[^SendNumArgsReg].
  	(liveRegsMask anyMask: (cogit registerMaskFor: ClassReg)) ifFalse:
  		[^ClassReg].
  	(liveRegsMask anyMask: (cogit registerMaskFor: ReceiverResultReg)) ifFalse:
  		[^ReceiverResultReg].
  	^nil!

Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateTwoRegistersInto: (in category 'simulation stack') -----
+ allocateTwoRegistersInto: binaryBlock
+ 	| topRegistersMask rTop rNext |
+ 	topRegistersMask := 0.
+ 	self ssTop type = SSRegister ifTrue: 
+ 		[ topRegistersMask := self registerMaskFor: (rTop := self ssTop register)].
+ 	(self ssValue: 1) type = SSRegister ifTrue: 
+ 		[ topRegistersMask := topRegistersMask bitOr: (self registerMaskFor: (rNext := (self ssValue: 1) register))].
+ 	(rTop notNil and: [rNext notNil]) ifTrue: 
+ 		[ ^ binaryBlock value: rTop value: rNext ].
+ 	
+ 	rTop ifNotNil:
+ 		[ rNext := backEnd availableRegisterOrNilFor: (self liveRegisters bitOr: topRegistersMask).
+ 		rNext ifNil: 
+ 			[ rNext := backEnd availableRegisterOrNilFor: topRegistersMask. 
+ 			self assert: rNext notNil.
+ 			self ssAllocateRequiredRegMask: rNext upThrough: simStackPtr - 1 ].
+ 		^ binaryBlock value: rTop value: rNext ].
+ 	
+ 	rNext ifNotNil:
+ 		[ rTop := backEnd availableRegisterOrNilFor: (self liveRegisters bitOr: topRegistersMask).
+ 		rTop ifNil: 
+ 			[ rTop := backEnd availableRegisterOrNilFor: topRegistersMask. 
+ 			self assert: rTop notNil.
+ 			self ssAllocateRequiredRegMask: rTop upThrough: simStackPtr - 2 ].
+ 		^ binaryBlock value: rTop value: rNext ].
+ 	
+ 	rTop := backEnd availableRegisterOrNilFor: self liveRegisters.
+ 	topRegistersMask := rTop ifNotNil: [ self registerMaskFor: rTop ] ifNil: [0].
+ 	rNext := backEnd availableRegisterOrNilFor: (self liveRegisters bitOr: topRegistersMask).
+ 	(rTop notNil and: [ rNext notNil ]) ifTrue: 
+ 		[ ^ binaryBlock value: rTop value: rNext ].
+ 	
+ 	rTop ifNil: [ ^ self spillTwoRegistersInto: binaryBlock ].
+ 	
+ 	"rNext isNil. rTop is allocated"
+ 	rNext := backEnd availableRegisterOrNilFor: topRegistersMask. 
+ 	self assert: rNext notNil.
+ 	self ssAllocateRequiredRegMask: rNext upThrough: simStackPtr - 1.
+ 	^ binaryBlock value: rTop value: rNext 
+ 	!

Item was changed:
  ----- Method: StackToRegisterMappingCogit>>genBinaryVarOpVarInlinePrimitive: (in category 'inline primitive generators') -----
  genBinaryVarOpVarInlinePrimitive: prim
  	"Var op var version of binary inline primitives."
  	"SistaV1: 248		11111000 	iiiiiiii		mjjjjjjj		Call Primitive #iiiiiiii + (jjjjjjj * 256) m=1 means inlined primitive, no hard return after execution.
  	 See EncoderForSistaV1's class comment and StackInterpreter>>#binaryInlinePrimitive:"
  	| ra rr adjust |
+ 	self allocateTwoRegistersInto: [:rTop :rNext | ra := rTop. rr := rNext ].
+ 	(rr = ReceiverResultReg or: [ra = ReceiverResultReg]) ifTrue: [ optStatus isReceiverResultRegLive: false ].
- 	(rr := backEnd availableRegisterOrNilFor: self liveRegisters) ifNil:
- 		[self ssAllocateRequiredReg:
- 			(rr := optStatus isReceiverResultRegLive
- 					ifTrue: [Arg0Reg]
- 					ifFalse: [ReceiverResultReg])].
- 	(ra := backEnd availableRegisterOrNilFor: (self liveRegisters bitOr: (self registerMaskFor: rr))) ifNil:
- 		[self ssAllocateRequiredReg: (ra := Arg1Reg)].
- 	(rr = ReceiverResultReg or: [ra = ReceiverResultReg]) ifTrue:
- 		[optStatus isReceiverResultRegLive: false].
  	self ssTop popToReg: ra.
  	self ssPop: 1.
  	self ssTop popToReg: rr.
  	self ssPop: 1.
  	prim caseOf: {
  		"0 through 6, +, -, *, /, //, \\, quo:, SmallInteger op SmallInteger => SmallInteger, no overflow"
  		[0]	->	[objectRepresentation genRemoveSmallIntegerTagsInScratchReg: ra.
  				 self AddR: ra R: rr].
  		[1]	->	[self SubR: ra R: rr.
  				 objectRepresentation genAddSmallIntegerTagsTo: rr].
  		[2]	->	[objectRepresentation genRemoveSmallIntegerTagsInScratchReg: rr.
  				 objectRepresentation genShiftAwaySmallIntegerTagsInScratchReg: ra.
  				 self MulR: ra R: rr.
  				 objectRepresentation genAddSmallIntegerTagsTo: rr].
  
  		"2016 through 2019, bitAnd:, bitOr:, bitXor, bitShift:, SmallInteger op SmallInteger => SmallInteger, no overflow"
  
  		"2032	through 2037, >, <, >=, <=. =, ~=, SmallInteger op SmallInteger => Boolean (flags?? then in jump bytecodes if ssTop is a flags value, just generate the instruction!!!!)"
  		[32] -> [ self CmpR: rr R: ra.
  				self genBinaryInlineComparison: JumpGreater opFalse: JumpLess destReg: rr ].
  		[33] -> [ self CmpR: rr R: ra.
  				self genBinaryInlineComparison: JumpLess opFalse: JumpGreater destReg: rr ].
  		[34] -> [ self CmpR: rr R: ra.
  				self genBinaryInlineComparison: JumpGreaterOrEqual opFalse: JumpLessOrEqual destReg: rr ].
  		[35] -> [ self CmpR: rr R: ra.
  				self genBinaryInlineComparison: JumpLessOrEqual opFalse: JumpGreaterOrEqual destReg: rr ].
  		[36] -> [ self CmpR: rr R: ra.
  				self genBinaryInlineComparison: JumpZero opFalse: JumpNonZero destReg: rr ].
  		[37] -> [ self CmpR: rr R: ra.
  				self genBinaryInlineComparison: JumpNonZero opFalse: JumpZero destReg: rr ].
  
  		"2064	through 2068, Pointer Object>>at:, Byte Object>>at:, Short16 Word Object>>at: LongWord32 Object>>at: Quad64Word Object>>at:. obj op 0-rel SmallInteger => oop"
  		[64] ->	[objectRepresentation genConvertSmallIntegerToIntegerInReg: ra.
  				adjust := (objectMemory baseHeaderSize >> objectMemory shiftForWord) - 1. "shift by baseHeaderSize and then move from 1 relative to zero relative"
  				adjust ~= 0 ifTrue: [ self AddCq: adjust R: ra. ]. 
  				self MoveXwr: ra R: rr R: rr ].
  		[65] ->	[objectRepresentation genConvertSmallIntegerToIntegerInReg: ra.
  				adjust := objectMemory baseHeaderSize - 1. "shift by baseHeaderSize and then move from 1 relative to zero relative"
  				self AddCq: adjust R: ra.
  				self MoveXbr: ra R: rr R: rr.
  				objectRepresentation genConvertIntegerToSmallIntegerInReg: rr]
  
  	}
  	otherwise: [^EncounteredUnknownBytecode].
  	self ssPushRegister: rr.
  	^0!

Item was added:
+ ----- Method: StackToRegisterMappingCogit>>spillTwoRegistersInto: (in category 'simulation stack') -----
+ spillTwoRegistersInto: binaryBlock
+ 	"Any occurrences on the stack of the register must be
+ 	 flushed, and hence any values colder than them stack."
+ 	<var: #desc type: #'CogSimStackEntry *'>
+ 	| r1 r2 index |
+ 	index := simSpillBase max: 0.
+ 	[r1 notNil and: [r2 notNil and: [index < simStackPtr]]] whileTrue:
+ 		[| desc |
+ 		 desc := self simStackAt: index.
+ 		 desc type = SSRegister ifTrue:
+ 			[ r1
+ 				ifNil: [r1 := desc register]
+ 				ifNotNil: [r1 ~= desc register ifTrue:
+ 							[r2 := desc register]]].
+ 		 index := index + 1].
+ 	self assert: (r1 notNil and: [r2 notNil]).
+ 	self ssAllocateRequiredReg: r1 and: r2.
+ 	^binaryBlock value: r1 value: r2!