[Vm-dev] VM Maker: VMMaker.oscog-eem.1189.mcz
commits at source.squeak.org
commits at source.squeak.org
Mon Apr 13 22:53:31 UTC 2015
Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1189.mcz
==================== Summary ====================
Name: VMMaker.oscog-eem.1189
Author: eem
Time: 13 April 2015, 3:51:49.43 pm
UUID: 592df209-8c8c-467b-b0df-a5195f376aa6
Ancestors: VMMaker.oscog-cb.1188
StackDepthFinder needs to implement doNop for
in-image compilation of ScUnsafeOperationTest methods.
allocateTwoRegistersInto: et al must be marked
at <inline: true> for slang to do its thang.
=============== Diff against VMMaker.oscog-cb.1188 ===============
Item was added:
+ ----- Method: StackDepthFinder>>doNop (in category 'instruction decoding') -----
+ doNop
+ "do nothing ;-)"!
Item was changed:
----- Method: StackToRegisterMappingCogit>>allocateThreeRegistersInto:thirdIsReceiver: (in category 'simulation stack') -----
allocateThreeRegistersInto: trinaryBlock thirdIsReceiver: thirdIsReceiver
+ <inline: true>
| topRegistersMask rTop rNext rThird |
topRegistersMask := 0.
(self ssTop type = SSRegister and: [ thirdIsReceiver not or: [ self ssTop register ~= ReceiverResultReg ] ]) ifTrue:
[ topRegistersMask := self registerMaskFor: (rTop := self ssTop register)].
((self ssValue: 1) type = SSRegister and: [ thirdIsReceiver not or: [ (self ssValue: 1) register ~= ReceiverResultReg ] ]) ifTrue:
[ topRegistersMask := topRegistersMask bitOr: (self registerMaskFor: (rNext := (self ssValue: 1) register))].
((self ssValue: 2) type = SSRegister and: [thirdIsReceiver not or: [ (self ssValue: 2) register = ReceiverResultReg ] ]) ifTrue:
[ topRegistersMask := topRegistersMask bitOr: (self registerMaskFor: (rThird := (self ssValue: 2) register))].
rThird ifNil:
[ thirdIsReceiver
ifTrue:
[ rThird := ReceiverResultReg. "Free ReceiverResultReg if it was not free"
(self register: ReceiverResultReg isInMask: self liveRegisters) ifTrue:
[ self ssAllocateRequiredReg: ReceiverResultReg ].
optStatus isReceiverResultRegLive: false ]
ifFalse: [ rThird := self allocateRegisterNotConflictingWith: topRegistersMask ].
topRegistersMask := topRegistersMask bitOr: (self registerMaskFor: rThird) ].
rTop ifNil: [
rTop := self allocateRegisterNotConflictingWith: topRegistersMask.
topRegistersMask := topRegistersMask bitOr: (self registerMaskFor: rTop) ].
rNext ifNil: [ rNext := self allocateRegisterNotConflictingWith: topRegistersMask ].
^ trinaryBlock value: rTop value: rNext value: rThird
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>allocateTwoRegistersInto: (in category 'simulation stack') -----
allocateTwoRegistersInto: binaryBlock
+ <inline: true>
| topRegistersMask rTop rNext |
topRegistersMask := 0.
self ssTop type = SSRegister ifTrue:
[ topRegistersMask := self registerMaskFor: (rTop := self ssTop register)].
(self ssValue: 1) type = SSRegister ifTrue:
[ topRegistersMask := topRegistersMask bitOr: (self registerMaskFor: (rNext := (self ssValue: 1) register))].
rTop ifNil: [ rTop := self allocateRegisterNotConflictingWith: topRegistersMask ].
rNext ifNil: [ rNext := self allocateRegisterNotConflictingWith: (self registerMaskFor: rTop) ].
^ binaryBlock value: rTop value: rNext
!
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