[Vm-dev] New Cog VMs available
eliot.miranda at gmail.com
Thu Apr 16 23:50:59 UTC 2015
... at http://www.mirandabanda.org/files/Cog/VM/VM.r3311/.
These should fix the regression introduced by the map changes in 3308. They certainly fix the two crashes I've looked at, one an update of a squeak trunk image and the other the startup of recent Newspeak images. Apologies for the inconvenience.
CogVM binaries as per VMMaker.oscog-eem.1204/r3311
Fix regression in map machinery due to adding AnnotationExtension scheme.
findMapLocationForMcpc:inMethod: must not be confused by IsDisplacementX2N
bytes. This is likely the cause of the recent crashes with r3308 and earlier.
Introduce marryFrameCopiesTemps and use it to
not copy temps in Spur context creation trampolines.
Change initial usage counts to keep more recently jitted methods around for
longer, and do *not* throw away PICs in freeOlderMethodsForCompaction, so that
there's a better chance of Sista finding send and branch data for the tripping
extendedPushBytecode /does/ need a frame.
Don't save the header in a scratch register unless
it is useful to do so in the Spur at:[put:] primitives.
Fix slip in genGetNumBytesOf:into:. And notice that
genGetFormatOf:into:baseHeaderIntoScratch: et al can use byte access
to get at format, as intended in the Spur header design.
Fix unlinking dynamic super sends.
Reduce false positives in access control violation reporting by marking the
super send we actually use as privileged. Remove unused Newspeak bytecodes.
Fix code generation bug surfaced by inline primitives. On x86 movb N(%reg),%rl
can only store into al, bl, cl & dl, whereas movzbl can store into any reg. On
ARM move byte also zero-extends. So change definition of MoveMbrR to always
zero-extend, use movzbl on x86 and remove all the MoveCq: 0 R: used to zero the
bits of the target of a MoveMb:r:R:. And now that we have
genGetNumSlotsOf:into:, use it.
Fix a slip in genTrinaryInlinePrimitive:, meet constraint that the target must
be in ReceiverResultReg, and do a better job of register allocation there-in.
Do dead code elimination for the branch following an inlined comparison (this
is done in genBinaryInlineComparison:opFalse:destReg: copying the scheme in
Do register allocation in the right place in genUnaryInlinePrimitive:.
Fix overflow slot access in genGetNumSlotsOf:into: et al.
Fix several slips in inline primitive generation: Object>>at:put: needs to
include a store check. Some register allocation code was wrong. Some results
needed converting to SmallIntegers and recording results as pushed on the sim
Change callPrimitiveBytecode to genCallPrimitiveBytecode in the Cogit.
remove the misnomer genConvertIntegerToSmallIntegerInScratchReg:
Type of AbstractInstruction opcode must be unsigned now that we have
more than 128 opcodes (XCHGRR pushed things over the top).
Lay the groundwork for 32-bit intra-zone jumps and calls on ARM by introducing
CallFull and JumpFull (and rewrites thereof) that are expected to span the full
address space, leaving Call/JumpLong to span merely the 16mb code zone. On x86
CallFull and JumpFull simply default to Call/JumpLong.
Replace bytecode trapIfNotInstanceOf by jumpIfNotInstanceOfOrPop.
Rewrote the JIT logic for traps to be able to write trap trampolines calls at
the end of the cogMethod.
Refactor the slot store and store check machinery to take an inFrame: argument
and hence deal with the store check in genInnerPrimitiveAtPut: on ARM.
Fix limitation with MoveRXbrR; can only do movb from
%al through %dl, so swap with %eax around movb.
Fix mistake with genGetNumBytesOf:into: by refactoring
and hence fetching and subtracting only odd bits of format.
Correct the in-line primitive SmallInteger comparisons; CmpXR is confusing ;-)
Fix var op var unsafe byte at:. Result must be converted to SmallInteger.
Correct the generated Slang for the new register allocation code by adding a
read-before-written pass to C generation that initializes variables
read-before-written with 0 (the C equivalent of nil).
fix a bug where sometimes register allocation was marking ReceiverResultReg as
dead whereas it was still alive.
Added some abstraction over register allocation. This is now used in inline
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