[Vm-dev] VM Maker: VMMaker.oscog-eem.1549.mcz
commits at source.squeak.org
commits at source.squeak.org
Sat Dec 5 00:21:31 UTC 2015
Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1549.mcz
==================== Summary ====================
Name: VMMaker.oscog-eem.1549
Author: eem
Time: 4 December 2015, 4:19:50.516 pm
UUID: 99726a9e-1891-4707-90a8-b4df377175aa
Ancestors: VMMaker.oscog-eem.1548
x64 Cogit: rationalise concretize"Op"RR into two routines in both x64 and x86.
Implement more Spur64Bit obj rep machinery.
=============== Diff against VMMaker.oscog-eem.1548 ===============
Item was removed:
- ----- Method: CogIA32Compiler>>concretizeAddRR (in category 'generate machine code') -----
- concretizeAddRR
- "Will get inlined into concretizeAt: switch."
- <inline: true>
- | regLHS regRHS |
- regLHS := self concreteRegister: (operands at: 0).
- regRHS := self concreteRegister: (operands at: 1).
- machineCode
- at: 0 put: 16r03;
- at: 1 put: (self mod: ModReg RM: regLHS RO: regRHS).
- ^machineCodeSize := 2!
Item was removed:
- ----- Method: CogIA32Compiler>>concretizeAndRR (in category 'generate machine code') -----
- concretizeAndRR
- "Will get inlined into concretizeAt: switch."
- <inline: true>
- | regLHS regRHS |
- regLHS := self concreteRegister: (operands at: 0).
- regRHS := self concreteRegister: (operands at: 1).
- machineCode
- at: 0 put: 16r23;
- at: 1 put: (self mod: ModReg RM: regLHS RO: regRHS).
- ^machineCodeSize := 2!
Item was removed:
- ----- Method: CogIA32Compiler>>concretizeCmpRR (in category 'generate machine code') -----
- concretizeCmpRR
- "Will get inlined into concretizeAt: switch."
- <inline: true>
- | regLHS regRHS |
- "CmpRR RHS LHS computes LHS - RHS, i.e. apparently reversed. You have to think subtract."
- regRHS := self concreteRegister: (operands at: 0).
- regLHS := self concreteRegister: (operands at: 1).
- machineCode
- at: 0 put: 16r39;
- at: 1 put: (self mod: ModReg RM: regLHS RO: regRHS).
- ^machineCodeSize := 2!
Item was removed:
- ----- Method: CogIA32Compiler>>concretizeMoveRR (in category 'generate machine code') -----
- concretizeMoveRR
- "Will get inlined into concretizeAt: switch."
- <inline: true>
- | srcReg destReg |
- srcReg := self concreteRegister: (operands at: 0).
- destReg := self concreteRegister: (operands at: 1).
- machineCode
- at: 0 put: 16r89;
- at: 1 put: (self mod: ModReg RM: destReg RO: srcReg).
- ^machineCodeSize := 2!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeOpRR: (in category 'generate machine code') -----
+ concretizeOpRR: opcode
+ | regLHS regRHS |
+ regLHS := self concreteRegister: (operands at: 0).
+ regRHS := self concreteRegister: (operands at: 1).
+ machineCode
+ at: 0 put: opcode;
+ at: 1 put: (self mod: ModReg RM: regLHS RO: regRHS).
+ ^machineCodeSize := 2!
Item was removed:
- ----- Method: CogIA32Compiler>>concretizeOrRR (in category 'generate machine code') -----
- concretizeOrRR
- "Will get inlined into concretizeAt: switch."
- <inline: true>
- | regLHS regRHS |
- regLHS := self concreteRegister: (operands at: 0).
- regRHS := self concreteRegister: (operands at: 1).
- machineCode
- at: 0 put: 16r0B;
- at: 1 put: (self mod: ModReg RM: regLHS RO: regRHS).
- ^machineCodeSize := 2!
Item was added:
+ ----- Method: CogIA32Compiler>>concretizeReverseOpRR: (in category 'generate machine code') -----
+ concretizeReverseOpRR: opcode
+ | regLHS regRHS |
+ regRHS := self concreteRegister: (operands at: 0).
+ regLHS := self concreteRegister: (operands at: 1).
+ machineCode
+ at: 0 put: opcode;
+ at: 1 put: (self mod: ModReg RM: regLHS RO: regRHS).
+ ^machineCodeSize := 2!
Item was removed:
- ----- Method: CogIA32Compiler>>concretizeSubRR (in category 'generate machine code') -----
- concretizeSubRR
- "Will get inlined into concretizeAt: switch."
- <inline: true>
- | regLHS regRHS |
- regLHS := self concreteRegister: (operands at: 0).
- regRHS := self concreteRegister: (operands at: 1).
- machineCode
- at: 0 put: 16r2B;
- at: 1 put: (self mod: ModReg RM: regLHS RO: regRHS).
- ^machineCodeSize := 2!
Item was removed:
- ----- Method: CogIA32Compiler>>concretizeXorRR (in category 'generate machine code') -----
- concretizeXorRR
- "Will get inlined into concretizeAt: switch."
- <inline: true>
- | regLHS regRHS |
- regLHS := self concreteRegister: (operands at: 0).
- regRHS := self concreteRegister: (operands at: 1).
- machineCode
- at: 0 put: 16r33;
- at: 1 put: (self mod: ModReg RM: regLHS RO: regRHS).
- ^machineCodeSize := 2!
Item was changed:
----- Method: CogIA32Compiler>>dispatchConcretize (in category 'generate machine code') -----
dispatchConcretize
"Attempt to generate concrete machine code for the instruction at address.
This is the inner dispatch of concretizeAt: actualAddress which exists only
to get around the branch size limits in the SqueakV3 (blue book derived)
bytecode set."
<returnTypeC: #void>
opcode caseOf: {
"Noops & Pseudo Ops"
[Label] -> [^self concretizeLabel].
[AlignmentNops] -> [^self concretizeAlignmentNops].
[Fill16] -> [^self concretizeFill16].
[Fill32] -> [^self concretizeFill32].
[FillFromWord] -> [^self concretizeFillFromWord].
[Nop] -> [^self concretizeNop].
"Specific Control/Data Movement"
[CDQ] -> [^self concretizeCDQ].
[IDIVR] -> [^self concretizeIDIVR].
[IMULRR] -> [^self concretizeMulRR].
[CPUID] -> [^self concretizeCPUID].
[CMPXCHGAwR] -> [^self concretizeCMPXCHGAwR].
[CMPXCHGMwrR] -> [^self concretizeCMPXCHGMwrR].
[LFENCE] -> [^self concretizeFENCE: 5].
[MFENCE] -> [^self concretizeFENCE: 6].
[SFENCE] -> [^self concretizeFENCE: 7].
[LOCK] -> [^self concretizeLOCK].
[XCHGAwR] -> [^self concretizeXCHGAwR].
[XCHGMwrR] -> [^self concretizeXCHGMwrR].
[XCHGRR] -> [^self concretizeXCHGRR].
"Control"
[Call] -> [^self concretizeCall].
[CallFull] -> [^self concretizeCall].
[JumpR] -> [^self concretizeJumpR].
[JumpFull] -> [^self concretizeJumpLong].
[JumpLong] -> [^self concretizeJumpLong].
[JumpLongZero] -> [^self concretizeConditionalJump: 16r4].
[JumpLongNonZero] -> [^self concretizeConditionalJump: 16r5].
[Jump] -> [^self concretizeJump].
"Table B-1 Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture"
[JumpZero] -> [^self concretizeConditionalJump: 16r4].
[JumpNonZero] -> [^self concretizeConditionalJump: 16r5].
[JumpNegative] -> [^self concretizeConditionalJump: 16r8].
[JumpNonNegative] -> [^self concretizeConditionalJump: 16r9].
[JumpOverflow] -> [^self concretizeConditionalJump: 16r0].
[JumpNoOverflow] -> [^self concretizeConditionalJump: 16r1].
[JumpCarry] -> [^self concretizeConditionalJump: 16r2].
[JumpNoCarry] -> [^self concretizeConditionalJump: 16r3].
[JumpLess] -> [^self concretizeConditionalJump: 16rC].
[JumpGreaterOrEqual] -> [^self concretizeConditionalJump: 16rD].
[JumpGreater] -> [^self concretizeConditionalJump: 16rF].
[JumpLessOrEqual] -> [^self concretizeConditionalJump: 16rE].
[JumpBelow] -> [^self concretizeConditionalJump: 16r2].
[JumpAboveOrEqual] -> [^self concretizeConditionalJump: 16r3].
[JumpAbove] -> [^self concretizeConditionalJump: 16r7].
[JumpBelowOrEqual] -> [^self concretizeConditionalJump: 16r6].
[JumpFPEqual] -> [^self concretizeConditionalJump: 16r4].
[JumpFPNotEqual] -> [^self concretizeConditionalJump: 16r5].
[JumpFPLess] -> [^self concretizeConditionalJump: 16r2].
[JumpFPGreaterOrEqual] -> [^self concretizeConditionalJump: 16r3].
[JumpFPGreater] -> [^self concretizeConditionalJump: 16r7].
[JumpFPLessOrEqual] -> [^self concretizeConditionalJump: 16r6].
[JumpFPOrdered] -> [^self concretizeConditionalJump: 16rB].
[JumpFPUnordered] -> [^self concretizeConditionalJump: 16rA].
[RetN] -> [^self concretizeRetN].
[Stop] -> [^self concretizeStop].
"Arithmetic"
[AddCqR] -> [^self concretizeAddCqR].
[AddCwR] -> [^self concretizeAddCwR].
+ [AddRR] -> [^self concretizeOpRR: 16r03].
- [AddRR] -> [^self concretizeAddRR].
[AddRdRd] -> [^self concretizeSEE2OpRdRd: 16r58].
[AndCqR] -> [^self concretizeAndCqR].
[AndCwR] -> [^self concretizeAndCwR].
+ [AndRR] -> [^self concretizeOpRR: 16r23].
- [AndRR] -> [^self concretizeAndRR].
[TstCqR] -> [^self concretizeTstCqR].
[CmpCqR] -> [^self concretizeCmpCqR].
[CmpCwR] -> [^self concretizeCmpCwR].
+ [CmpRR] -> [^self concretizeReverseOpRR: 16r39].
- [CmpRR] -> [^self concretizeCmpRR].
[CmpRdRd] -> [^self concretizeCmpRdRd].
[DivRdRd] -> [^self concretizeSEE2OpRdRd: 16r5E].
[MulRdRd] -> [^self concretizeSEE2OpRdRd: 16r59].
[OrCqR] -> [^self concretizeOrCqR].
[OrCwR] -> [^self concretizeOrCwR].
+ [OrRR] -> [^self concretizeOpRR: 16r0B].
- [OrRR] -> [^self concretizeOrRR].
[SubCqR] -> [^self concretizeSubCqR].
[SubCwR] -> [^self concretizeSubCwR].
+ [SubRR] -> [^self concretizeOpRR: 16r2B].
- [SubRR] -> [^self concretizeSubRR].
[SubRdRd] -> [^self concretizeSEE2OpRdRd: 16r5C].
[SqrtRd] -> [^self concretizeSqrtRd].
[XorCwR] -> [^self concretizeXorCwR].
+ [XorRR] -> [^self concretizeOpRR: 16r33].
- [XorRR] -> [^self concretizeXorRR].
[NegateR] -> [^self concretizeNegateR].
[LoadEffectiveAddressMwrR] -> [^self concretizeLoadEffectiveAddressMwrR].
[ArithmeticShiftRightCqR] -> [^self concretizeArithmeticShiftRightCqR].
[LogicalShiftRightCqR] -> [^self concretizeLogicalShiftRightCqR].
[LogicalShiftLeftCqR] -> [^self concretizeLogicalShiftLeftCqR].
[ArithmeticShiftRightRR] -> [^self concretizeArithmeticShiftRightRR].
[LogicalShiftLeftRR] -> [^self concretizeLogicalShiftLeftRR].
"Data Movement"
[MoveCqR] -> [^self concretizeMoveCqR].
[MoveCwR] -> [^self concretizeMoveCwR].
+ [MoveRR] -> [^self concretizeReverseOpRR: 16r89].
- [MoveRR] -> [^self concretizeMoveRR].
[MoveAwR] -> [^self concretizeMoveAwR].
[MoveRAw] -> [^self concretizeMoveRAw].
[MoveAbR] -> [^self concretizeMoveAbR].
[MoveRAb] -> [^self concretizeMoveRAb].
[MoveMbrR] -> [^self concretizeMoveMbrR].
[MoveRMbr] -> [^self concretizeMoveRMbr].
[MoveM16rR] -> [^self concretizeMoveM16rR].
[MoveM64rRd] -> [^self concretizeMoveM64rRd].
[MoveMwrR] -> [^self concretizeMoveMwrR].
[MoveXbrRR] -> [^self concretizeMoveXbrRR].
[MoveRXbrR] -> [^self concretizeMoveRXbrR].
[MoveXwrRR] -> [^self concretizeMoveXwrRR].
[MoveRXwrR] -> [^self concretizeMoveRXwrR].
[MoveRMwr] -> [^self concretizeMoveRMwr].
[MoveRdM64r] -> [^self concretizeMoveRdM64r].
[PopR] -> [^self concretizePopR].
[PushR] -> [^self concretizePushR].
[PushCq] -> [^self concretizePushCq].
[PushCw] -> [^self concretizePushCw].
[PrefetchAw] -> [^self concretizePrefetchAw].
"Conversion"
[ConvertRRd] -> [^self concretizeConvertRRd] }!
Item was added:
+ ----- Method: CogObjectRepresentationFor64BitSpur>>genAddSmallIntegerTagsTo: (in category 'compile abstract instructions') -----
+ genAddSmallIntegerTagsTo: aRegister
+ cogit AddCq: 1 R: aRegister.
+ ^0!
Item was removed:
- ----- Method: CogX64Compiler>>concretizeAddRR (in category 'generate machine code') -----
- concretizeAddRR
- "Will get inlined into concretizeAt: switch."
- <inline: true>
- | regLHS regRHS |
- regLHS := self concreteRegister: (operands at: 0).
- regRHS := self concreteRegister: (operands at: 1).
- machineCode
- at: 0 put: (self rexR: regRHS x: 0 b: regLHS);
- at: 1 put: 16r03;
- at: 2 put: (self mod: ModReg RM: regLHS RO: regRHS).
- ^machineCodeSize := 3!
Item was removed:
- ----- Method: CogX64Compiler>>concretizeAndRR (in category 'generate machine code') -----
- concretizeAndRR
- "Will get inlined into concretizeAt: switch."
- <inline: true>
- | regLHS regRHS |
- regLHS := self concreteRegister: (operands at: 0).
- regRHS := self concreteRegister: (operands at: 1).
- machineCode
- at: 0 put: (self rexR: regRHS x: 0 b: regLHS);
- at: 1 put: 16r23;
- at: 2 put: (self mod: ModReg RM: regLHS RO: regRHS).
- ^machineCodeSize := 3!
Item was removed:
- ----- Method: CogX64Compiler>>concretizeCmpRR (in category 'generate machine code') -----
- concretizeCmpRR
- "Will get inlined into concretizeAt: switch."
- <inline: true>
- | regLHS regRHS |
- "CmpRR RHS LHS computes LHS - RHS, i.e. apparently reversed. You have to think subtract."
- regRHS := self concreteRegister: (operands at: 0).
- regLHS := self concreteRegister: (operands at: 1).
- machineCode
- at: 0 put: (self rexR: regRHS x: 0 b: regLHS);
- at: 1 put: 16r39;
- at: 2 put: (self mod: ModReg RM: regLHS RO: regRHS).
- ^machineCodeSize := 3!
Item was removed:
- ----- Method: CogX64Compiler>>concretizeMoveRR (in category 'generate machine code') -----
- concretizeMoveRR
- "Will get inlined into concretizeAt: switch."
- <inline: true>
- | srcReg destReg |
- srcReg := self concreteRegister: (operands at: 0).
- destReg := self concreteRegister: (operands at: 1).
- machineCode
- at: 0 put: (self rexR: srcReg x: 0 b: destReg);
- at: 1 put: 16r89;
- at: 2 put: (self mod: ModReg RM: destReg RO: srcReg).
- ^machineCodeSize := 3!
Item was added:
+ ----- Method: CogX64Compiler>>concretizeOpRR: (in category 'generate machine code') -----
+ concretizeOpRR: opcode
+ | regLHS regRHS |
+ regLHS := self concreteRegister: (operands at: 0).
+ regRHS := self concreteRegister: (operands at: 1).
+ machineCode
+ at: 0 put: (self rexR: regRHS x: 0 b: regLHS);
+ at: 1 put: opcode;
+ at: 2 put: (self mod: ModReg RM: regLHS RO: regRHS).
+ ^machineCodeSize := 3!
Item was added:
+ ----- Method: CogX64Compiler>>concretizeReverseOpRR: (in category 'generate machine code') -----
+ concretizeReverseOpRR: opcode
+ | regLHS regRHS |
+ "CmpRR/MoveRR RHS LHS computes LHS - RHS, i.e. apparently reversed. You have to think subtract."
+ regRHS := self concreteRegister: (operands at: 0).
+ regLHS := self concreteRegister: (operands at: 1).
+ machineCode
+ at: 0 put: (self rexR: regRHS x: 0 b: regLHS);
+ at: 1 put: opcode;
+ at: 2 put: (self mod: ModReg RM: regLHS RO: regRHS).
+ ^machineCodeSize := 3!
Item was removed:
- ----- Method: CogX64Compiler>>concretizeSubRR (in category 'generate machine code') -----
- concretizeSubRR
- "Will get inlined into concretizeAt: switch."
- <inline: true>
- | regLHS regRHS |
- regLHS := self concreteRegister: (operands at: 0).
- regRHS := self concreteRegister: (operands at: 1).
- machineCode
- at: 0 put: (self rexR: regRHS x: 0 b: regLHS);
- at: 1 put: 16r2b;
- at: 2 put: (self mod: ModReg RM: regLHS RO: regRHS).
- ^machineCodeSize := 3!
Item was removed:
- ----- Method: CogX64Compiler>>concretizeXorRR (in category 'generate machine code') -----
- concretizeXorRR
- "Will get inlined into concretizeAt: switch."
- <inline: true>
- | regLHS regRHS |
- regLHS := self concreteRegister: (operands at: 0).
- regRHS := self concreteRegister: (operands at: 1).
- machineCode
- at: 0 put: (self rexR: regRHS x: 0 b: regLHS);
- at: 1 put: 16r33;
- at: 2 put: (self mod: ModReg RM: regLHS RO: regRHS).
- ^machineCodeSize := 3!
Item was changed:
----- Method: CogX64Compiler>>dispatchConcretize (in category 'generate machine code') -----
dispatchConcretize
"Attempt to generate concrete machine code for the instruction at address.
This is the inner dispatch of concretizeAt: actualAddress which exists only
to get around the branch size limits in the SqueakV3 (blue book derived)
bytecode set."
<returnTypeC: #void>
opcode caseOf: {
"Noops & Pseudo Ops"
[Label] -> [^self concretizeLabel].
[AlignmentNops] -> [^self concretizeAlignmentNops].
[Fill16] -> [^self concretizeFill16].
[Fill32] -> [^self concretizeFill32].
[FillFromWord] -> [^self concretizeFillFromWord].
[Nop] -> [^self concretizeNop].
"Specific Control/Data Movement"
[CDQ] -> [^self concretizeCDQ].
[IDIVR] -> [^self concretizeIDIVR].
[IMULRR] -> [^self concretizeMulRR].
[CPUID] -> [^self concretizeCPUID].
[CMPXCHGAwR] -> [^self concretizeCMPXCHGAwR].
[CMPXCHGMwrR] -> [^self concretizeCMPXCHGMwrR].
[LFENCE] -> [^self concretizeFENCE: 5].
[MFENCE] -> [^self concretizeFENCE: 6].
[SFENCE] -> [^self concretizeFENCE: 7].
[LOCK] -> [^self concretizeLOCK].
[XCHGAwR] -> [^self concretizeXCHGAwR].
[XCHGMwrR] -> [^self concretizeXCHGMwrR].
[XCHGRR] -> [^self concretizeXCHGRR].
"Control"
[Call] -> [^self concretizeCall].
[CallFull] -> [^self concretizeCallFull].
[JumpR] -> [^self concretizeJumpR].
[JumpFull] -> [^self concretizeJumpFull].
[JumpLong] -> [^self concretizeJumpLong].
[JumpLongZero] -> [^self concretizeConditionalJump: 16r4].
[JumpLongNonZero] -> [^self concretizeConditionalJump: 16r5].
[Jump] -> [^self concretizeJump].
"Table B-1 Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture"
[JumpZero] -> [^self concretizeConditionalJump: 16r4].
[JumpNonZero] -> [^self concretizeConditionalJump: 16r5].
[JumpNegative] -> [^self concretizeConditionalJump: 16r8].
[JumpNonNegative] -> [^self concretizeConditionalJump: 16r9].
[JumpOverflow] -> [^self concretizeConditionalJump: 16r0].
[JumpNoOverflow] -> [^self concretizeConditionalJump: 16r1].
[JumpCarry] -> [^self concretizeConditionalJump: 16r2].
[JumpNoCarry] -> [^self concretizeConditionalJump: 16r3].
[JumpLess] -> [^self concretizeConditionalJump: 16rC].
[JumpGreaterOrEqual] -> [^self concretizeConditionalJump: 16rD].
[JumpGreater] -> [^self concretizeConditionalJump: 16rF].
[JumpLessOrEqual] -> [^self concretizeConditionalJump: 16rE].
[JumpBelow] -> [^self concretizeConditionalJump: 16r2].
[JumpAboveOrEqual] -> [^self concretizeConditionalJump: 16r3].
[JumpAbove] -> [^self concretizeConditionalJump: 16r7].
[JumpBelowOrEqual] -> [^self concretizeConditionalJump: 16r6].
[JumpFPEqual] -> [^self concretizeConditionalJump: 16r4].
[JumpFPNotEqual] -> [^self concretizeConditionalJump: 16r5].
[JumpFPLess] -> [^self concretizeConditionalJump: 16r2].
[JumpFPGreaterOrEqual] -> [^self concretizeConditionalJump: 16r3].
[JumpFPGreater] -> [^self concretizeConditionalJump: 16r7].
[JumpFPLessOrEqual] -> [^self concretizeConditionalJump: 16r6].
[JumpFPOrdered] -> [^self concretizeConditionalJump: 16rB].
[JumpFPUnordered] -> [^self concretizeConditionalJump: 16rA].
[RetN] -> [^self concretizeRetN].
[Stop] -> [^self concretizeStop].
"Arithmetic"
[AddCqR] -> [^self concretizeArithCqRWithRO: 0 raxOpcode: 15r05].
[AddCwR] -> [^self concretizeArithCwR: 16r03].
+ [AddRR] -> [^self concretizeOpRR: 16r03].
- [AddRR] -> [^self concretizeAddRR].
[AddRdRd] -> [^self concretizeSEE2OpRdRd: 16r58].
[AndCqR] -> [^self concretizeArithCqRWithRO: 4 raxOpcode: 16r25].
[AndCwR] -> [^self concretizeArithCwR: 16r23].
+ [AndRR] -> [^self concretizeOpRR: 16r23].
- [AndRR] -> [^self concretizeAndRR].
[TstCqR] -> [^self concretizeTstCqR].
[CmpCqR] -> [^self concretizeArithCqRWithRO: 7 raxOpcode: 16r3D].
[CmpCwR] -> [^self concretizeArithCwR: 16r39].
[CmpC32R] -> [^self concretizeCmpC32R].
+ [CmpRR] -> [^self concretizeReverseOpRR: 16r39].
- [CmpRR] -> [^self concretizeCmpRR].
[CmpRdRd] -> [^self concretizeCmpRdRd].
[DivRdRd] -> [^self concretizeSEE2OpRdRd: 16r5E].
[MulRdRd] -> [^self concretizeSEE2OpRdRd: 16r59].
[OrCqR] -> [^self concretizeArithCqRWithRO: 1 raxOpcode: 16r0D].
[OrCwR] -> [^self concretizeArithCwR: 16r0B].
+ [OrRR] -> [^self concretizeOpRR: 16r0B].
- [OrRR] -> [^self concretizeOrRR].
[SubCqR] -> [^self concretizeArithCqRWithRO: 5 raxOpcode: 16r2D].
[SubCwR] -> [^self concretizeArithCwR: 16r2B].
+ [SubRR] -> [^self concretizeOpRR: 16r2B].
- [SubRR] -> [^self concretizeSubRR].
[SubRdRd] -> [^self concretizeSEE2OpRdRd: 16r5C].
[SqrtRd] -> [^self concretizeSqrtRd].
[XorCwR] -> [^self concretizeArithCwR: 16r33].
+ [XorRR] -> [^self concretizeOpRR: 16r33].
- [XorRR] -> [^self concretizeXorRR].
[NegateR] -> [^self concretizeNegateR].
[LoadEffectiveAddressMwrR] -> [^self concretizeLoadEffectiveAddressMwrR].
[ArithmeticShiftRightCqR] -> [^self concretizeShiftCqRegOpcode: 7].
[LogicalShiftRightCqR] -> [^self concretizeShiftCqRegOpcode: 5].
[LogicalShiftLeftCqR] -> [^self concretizeShiftCqRegOpcode: 4].
[ArithmeticShiftRightRR] -> [^self concretizeShiftRegRegOpcode: 7].
[LogicalShiftLeftRR] -> [^self concretizeShiftRegRegOpcode: 4].
"Data Movement"
[MoveCqR] -> [^self concretizeMoveCqR].
[MoveCwR] -> [^self concretizeMoveCwR].
[MoveC32R] -> [^self concretizeMoveC32R].
+ [MoveRR] -> [^self concretizeReverseOpRR: 16r89].
- [MoveRR] -> [^self concretizeMoveRR].
[MoveAwR] -> [^self concretizeMoveAwR].
[MoveRAw] -> [^self concretizeMoveRAw].
[MoveAbR] -> [^self concretizeMoveAbR].
[MoveRAb] -> [^self concretizeMoveRAb].
[MoveMbrR] -> [^self concretizeMoveMbrR].
[MoveRMbr] -> [^self concretizeMoveRMbr].
[MoveM16rR] -> [^self concretizeMoveM16rR].
[MoveM64rRd] -> [^self concretizeMoveM64rRd].
[MoveMwrR] -> [^self concretizeMoveMwrR].
[MoveXbrRR] -> [^self concretizeMoveXbrRR].
[MoveRXbrR] -> [^self concretizeMoveRXbrR].
[MoveXwrRR] -> [^self concretizeMoveXwrRR].
[MoveRXwrR] -> [^self concretizeMoveRXwrR].
[MoveX32rRR] -> [^self concretizeMoveX32rRR].
[MoveRMwr] -> [^self concretizeMoveRMwr].
[MoveRdM64r] -> [^self concretizeMoveRdM64r].
[PopR] -> [^self concretizePopR].
[PushR] -> [^self concretizePushR].
[PushCq] -> [^self concretizePushCq].
[PushCw] -> [^self concretizePushCw].
[PrefetchAw] -> [^self concretizePrefetchAw].
"Conversion"
[ConvertRRd] -> [^self concretizeConvertRRd] }!
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