[Vm-dev] VM Maker: VMMaker.oscog-eem.1556.mcz

commits at source.squeak.org commits at source.squeak.org
Sat Dec 5 23:30:31 UTC 2015


Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1556.mcz

==================== Summary ====================

Name: VMMaker.oscog-eem.1556
Author: eem
Time: 5 December 2015, 3:28:47.468 pm
UUID: b50470c0-c306-40ed-96dc-aada552d93a4
Ancestors: VMMaker.oscog-eem.1555

Propitiate the Slang gods.

=============== Diff against VMMaker.oscog-eem.1555 ===============

Item was changed:
  ----- Method: CogIA32Compiler>>concretizeOpRR: (in category 'generate machine code') -----
+ concretizeOpRR: x86opcode
- concretizeOpRR: opcode
  	| regLHS regRHS |
  	regLHS := self concreteRegister: (operands at: 0).
  	regRHS := self concreteRegister: (operands at: 1).
  	machineCode
+ 		at: 0 put: x86opcode;
- 		at: 0 put: opcode;
  		at: 1 put: (self mod: ModReg RM: regLHS RO: regRHS).
  	^machineCodeSize := 2!

Item was changed:
  ----- Method: CogIA32Compiler>>concretizeReverseOpRR: (in category 'generate machine code') -----
+ concretizeReverseOpRR: x86opcode
- concretizeReverseOpRR: opcode
  	| regLHS regRHS |
  	regRHS := self concreteRegister: (operands at: 0).
  	regLHS := self concreteRegister: (operands at: 1).
  	machineCode
+ 		at: 0 put: x86opcode;
- 		at: 0 put: opcode;
  		at: 1 put: (self mod: ModReg RM: regLHS RO: regRHS).
  	^machineCodeSize := 2!

Item was changed:
  ----- Method: CogX64Compiler>>concretizeOpRR: (in category 'generate machine code') -----
+ concretizeOpRR: x64opcode
- concretizeOpRR: opcode
  	| regLHS regRHS |
  	regLHS := self concreteRegister: (operands at: 0).
  	regRHS := self concreteRegister: (operands at: 1).
  	machineCode
  		at: 0 put: (self rexR: regRHS x: 0 b: regLHS);
+ 		at: 1 put: x64opcode;
- 		at: 1 put: opcode;
  		at: 2 put: (self mod: ModReg RM: regLHS RO: regRHS).
  	^machineCodeSize := 3!

Item was changed:
  ----- Method: CogX64Compiler>>concretizeReverseOpRR: (in category 'generate machine code') -----
+ concretizeReverseOpRR: x64opcode
- concretizeReverseOpRR: opcode
  	| regLHS regRHS |
  	"CmpRR/MoveRR RHS LHS computes LHS - RHS, i.e. apparently reversed.  You have to think subtract."
  	regRHS := self concreteRegister: (operands at: 0).
  	regLHS := self concreteRegister: (operands at: 1).
  	machineCode
  		at: 0 put: (self rexR: regRHS x: 0 b: regLHS);
+ 		at: 1 put: x64opcode;
- 		at: 1 put: opcode;
  		at: 2 put: (self mod: ModReg RM: regLHS RO: regRHS).
  	^machineCodeSize := 3!



More information about the Vm-dev mailing list