[Vm-dev] VM Maker: VMMaker.oscog-eem.1563.mcz

commits at source.squeak.org commits at source.squeak.org
Mon Dec 7 06:45:56 UTC 2015


Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1563.mcz

==================== Summary ====================

Name: VMMaker.oscog-eem.1563
Author: eem
Time: 6 December 2015, 10:44:12.225 pm
UUID: 9e8be763-2d4a-4e2d-bf6a-c8a46c5499c0
Ancestors: VMMaker.oscog-eem.1562

x64 Cogit: 
implement MoveRdM64r

=============== Diff against VMMaker.oscog-eem.1562 ===============

Item was changed:
  ----- Method: CogX64Compiler>>computeMaximumSize (in category 'generate machine code') -----
(excessive size, no diff calculated)

Item was added:
+ ----- Method: CogX64Compiler>>concretizeMoveRdM64r (in category 'generate machine code') -----
+ concretizeMoveRdM64r
+ 	<inline: true>
+ 	| offset srcReg destReg skip |
+ 	srcReg := self concreteDPFPRegister: (operands at: 0).
+ 	offset := operands at: 1.
+ 	destReg := self concreteRegister: (operands at: 2).
+ 	machineCode at: 0 put: 16r66.
+ 	(srcReg <= 7 and: [destReg <= 7])
+ 		ifTrue: [skip := 0]
+ 		ifFalse: [machineCode at: (skip := 1) put: (self rexw: false r: srcReg x: 0 b: destReg)].
+ 	machineCode
+ 		at: skip + 1 put: 16r0f;
+ 		at: skip + 2 put: 16rd6.
+ 	offset = 0 ifTrue:
+ 		[(destReg bitAnd: 6) ~= RSP ifTrue:
+ 			[machineCode at: skip + 3 put: (self mod: ModRegInd RM: destReg RO: srcReg).
+ 			 ^machineCodeSize := skip + 4].
+ 		 (destReg bitAnd: 7) = RSP ifTrue: "RBP & R13 fall through"
+ 			[machineCode
+ 				at: skip + 3 put: (self mod: ModRegInd RM: destReg RO: srcReg);
+ 				at: skip + 4 put: (self s: SIB1 i: 4 b: destReg).
+ 			 ^machineCodeSize := skip + 5]].
+ 	(self isQuick: offset) ifTrue:
+ 		[(destReg bitAnd: 7) ~= RSP ifTrue:
+ 			[machineCode
+ 				at: skip + 3 put: (self mod: ModRegRegDisp8 RM: destReg RO: srcReg);
+ 				at: skip + 4 put: (offset bitAnd: 16rFF).
+ 			 ^machineCodeSize := skip + 5].
+ 		 machineCode
+ 			at: skip + 3 put: (self mod: ModRegRegDisp8 RM: destReg RO: srcReg);
+ 			at: skip + 4 put: (self s: SIB1 i: 4 b: destReg);
+ 			at: skip + 5 put: (offset bitAnd: 16rFF).
+ 		 ^machineCodeSize := skip + 6].
+ 	machineCode at: skip + 3 put: (self mod: ModRegRegDisp32 RM: destReg RO: srcReg).
+ 	(destReg bitAnd: 7) = RSP ifTrue:
+ 		[machineCode at: skip + 4 put: (self s: SIB1 i: 4 b: destReg).
+ 		 skip := skip + 1].
+ 	machineCode
+ 		at: skip + 4 put: (offset bitAnd: 16rFF);
+ 		at: skip + 5 put: (offset >> 8 bitAnd: 16rFF);
+ 		at: skip + 6 put: (offset >> 16 bitAnd: 16rFF);
+ 		at: skip + 7 put: (offset >> 24 bitAnd: 16rFF).
+ 	^machineCodeSize := skip + 8!

Item was changed:
  ----- Method: CogX64CompilerTests>>testMoveRdM64r (in category 'tests') -----
  testMoveRdM64r
  	"self new testMoveRdM64r"
  	self concreteCompilerClass xmmRegistersWithNamesDo:
  		[:sreg :srname|
  		self concreteCompilerClass registersWithNamesDo:
  			[:dreg :drname|
+ 			#(0 8 256 32760) do:
- 			((1 to: 19 by: 3) collect: [:po2| 2 raisedToInteger: po2]) do:
  				[:offset| | inst len |
  				inst := self gen: MoveRdM64r operand: sreg operand: offset operand: dreg.
  				len := inst concretizeAt: 0.
  				self processor
  					disassembleInstructionAt: 0
  					In: inst machineCode object
  					into: [:str :sz| | plainJane herIntended |
  						plainJane := self strip: str.
+ 						herIntended := 'movq ', srname,
+ 											(offset = 0
+ 												ifTrue: [', ']
+ 												ifFalse: [', 0x', ((offset printStringBase: 16 length: 16 padded: true))]),
+ 											'(', drname, ')'.
- 						herIntended := 'movq ', srname, ', 0x', (offset hex allButFirst: 3), '(', drname, ')'.
  						self assert: herIntended equals: plainJane.
+ 						self assert: len = sz]]]]
+ 
+ "| them it |
+ them := OrderedCollection new.
+ [(it := CogX64CompilerTests new) testMoveRdM64r]
+ 	on: AssertionFailure, TestResult failure
+ 	do: [:ex| | inst |
+ 		ex class == AssertionFailure
+ 			ifTrue:
+ 				[inst := ex signalerContext receiver.
+ 				it processor
+ 					disassembleInstructionAt: 0
+ 					In: inst machineCode object
+ 					into: [:str :sz| them addLast: (it strip: str)]]
+ 			ifFalse:
+ 				[ResumableTestFailure adoptInstance: ex].
+ 		ex resume].
+ them size"
+ "| them it |
+ them := OrderedCollection new.
+ [(it := CogX64CompilerTests new) testMoveRdM64r]
+ 	on: TestResult failure
+ 	do: [:ex| | ctxt |
+ 		ctxt := ex signalerContext findContextSuchThat: [:c| c selector == #assert:equals:]..
+ 		them addLast: {ctxt tempAt: 1. ctxt tempAt: 2}.
+ 		ResumableTestFailure adoptInstance: ex.
+ 		ex resume].
+ them size"!
- 						self assert: len = sz]]]]!

Item was changed:
  ----- Method: StackToRegisterMappingCogit>>genDoubleArithmetic:preOpCheck: (in category 'primitive generators') -----
  genDoubleArithmetic: arithmeticOperator preOpCheck: preOpCheckOrNil
  	"Receiver and arg in registers.
  	 Stack looks like
  		return address"
  	<var: #preOpCheckOrNil declareC: 'AbstractInstruction *(*preOpCheckOrNil)(int rcvrReg, int argReg)'>
  	| jumpFailClass jumpFailAlloc jumpFailCheck jumpImmediate jumpNonInt doOp |
  	<var: #jumpFailClass type: #'AbstractInstruction *'>
  	<var: #jumpFailAlloc type: #'AbstractInstruction *'>
  	<var: #jumpImmediate type: #'AbstractInstruction *'>
  	<var: #jumpNonInt type: #'AbstractInstruction *'>
  	<var: #jumpFailCheck type: #'AbstractInstruction *'>
  	<var: #doOp type: #'AbstractInstruction *'>
  	objectRepresentation genGetDoubleValueOf: ReceiverResultReg into: DPFPReg0.
  	self MoveR: Arg0Reg R: ClassReg.
  	jumpImmediate := objectRepresentation genJumpImmediate: Arg0Reg.
  	objectRepresentation genGetCompactClassIndexNonImmOf: Arg0Reg into: SendNumArgsReg.
  	objectRepresentation genCmpClassFloatCompactIndexR: SendNumArgsReg.
  	jumpFailClass := self JumpNonZero: 0.
  	objectRepresentation genGetDoubleValueOf: Arg0Reg into: DPFPReg1.
  	doOp := self Label.
  	preOpCheckOrNil ifNotNil:
  		[jumpFailCheck := self perform: preOpCheckOrNil with: DPFPReg0 with: DPFPReg1].
  	self gen: arithmeticOperator operand: DPFPReg1 operand: DPFPReg0.
  	jumpFailAlloc := objectRepresentation
  						genAllocFloatValue: DPFPReg0
  						into: SendNumArgsReg
  						scratchReg: ClassReg
  						scratchReg: TempReg.
  	self MoveR: SendNumArgsReg R: ReceiverResultReg.
  	self RetN: 0.
  	"We need to push the register args on two paths; this one and the interpreter primitive path.
  	But the interpreter primitive path won't unless regArgsHaveBeenPushed is false."
  	self assert: methodOrBlockNumArgs <= self numRegArgs.
  	jumpFailClass jmpTarget: self Label.
  	preOpCheckOrNil ifNotNil:
  		[jumpFailCheck jmpTarget: jumpFailClass getJmpTarget].
  	backEnd genPushRegisterArgsForNumArgs: methodOrBlockNumArgs scratchReg: SendNumArgsReg.
  	jumpFailClass := self Jump: 0.
  	jumpImmediate jmpTarget: self Label.
  	objectRepresentation smallIntegerIsOnlyImmediateType ifFalse:
+ 		[jumpNonInt := objectRepresentation genJumpNotSmallInteger: Arg0Reg scratch: TempReg].
- 		[jumpNonInt := objectRepresentation genJumpNotSmallInteger: Arg0Reg].
  	objectRepresentation genConvertSmallIntegerToIntegerInReg: ClassReg.
  	self ConvertR: ClassReg Rd: DPFPReg1.
  	self Jump: doOp.
  	jumpFailAlloc jmpTarget: self Label.
  	self compileFallbackToInterpreterPrimitive: 0.
  	jumpFailClass jmpTarget: self Label.
  	objectRepresentation smallIntegerIsOnlyImmediateType ifFalse:
  		[jumpNonInt jmpTarget: jumpFailClass getJmpTarget].
  	^0!



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