[Vm-dev] VM Maker: VMMaker.oscog-eem.1603.mcz

[commits at source.squeak.org]

Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1603.mcz

==================== Summary ====================

Name: VMMaker.oscog-eem.1603
Author: eem
Time: 16 December 2015, 7:09:36.295 pm
UUID: 70337b05-e1e3-418f-9fcd-8a7f72c9a082
Ancestors: VMMaker.oscog-eem.1602

x64 Cogit:

Fix stupidities in concretize[Call|Jump]Full (move absolute value, not value referenced by absolute address).

Delete the hack in the simulator that made this mistake "work".

Fix REX byte slip in concretizeMoveCwR.

=============== Diff against VMMaker.oscog-eem.1602 ===============

Item was changed:
  ----- Method: CogInLineLiteralsX64Compiler>>concretizeMoveCwR (in category 'generate machine code') -----
  concretizeMoveCwR
  	"Will get inlined into concretizeAt: switch."
  	<inline: true>
  	| value reg offset |
  	value := operands at: 0.
  	reg := self concreteRegister: (operands at: 1).
  	(self isAnInstruction: (cogit cCoerceSimple: value to: #'AbstractInstruction *')) ifTrue:
  		[value := (cogit cCoerceSimple: value to: #'AbstractInstruction *') address].
  	(cogit addressIsInCurrentCompilation: value) ifTrue:
  		[offset := value - (address + 7).
  		 machineCode
  			at: 0 put: (self rexR: reg x: 0 b: 0);
  			at: 1 put: 16r8D; "LoadEffectiveAddress"
  			at: 2 put: (self mod: ModRegInd RM: 5 RO: reg);
  			at: 3 put: (offset bitAnd: 16rFF);
  			at: 4 put: (offset >> 8 bitAnd: 16rFF);
  			at: 5 put: (offset >> 16 bitAnd: 16rFF);
  			at: 6 put: (offset >> 24 bitAnd: 16rFF).
  		^machineCodeSize := 7].
  	machineCode
+ 		at:  0 put: (self rexR: 0 x: 0 b: reg);
- 		at:  0 put: (self rexR: reg x: 0 b: reg);
  		at:  1 put: 16rB8 + (reg bitAnd: 7);
  		at:  2 put: (value bitAnd: 16rFF);
  		at:  3 put: (value >> 8 bitAnd: 16rFF);
  		at:  4 put: (value >> 16 bitAnd: 16rFF);
  		at:  5 put: (value >> 24 bitAnd: 16rFF);
  		at:  6 put: (value >> 32 bitAnd: 16rFF);
  		at:  7 put: (value >> 40 bitAnd: 16rFF);
  		at:  8 put: (value >> 48 bitAnd: 16rFF);
  		at:  9 put: (value >> 56 bitAnd: 16rFF).
  	opcode = MoveCqR ifTrue:
  		[^machineCodeSize := 10].
  	"Add a nop to disambiguate between MoveCwR/PushCwR and ArithCwR, which ends with a (self mod: ModReg RM: 0 RO: 0)"
  	machineCode at: 10 put: 16r90.
  	self assert: (self mod: ModReg RM: 0 RO: 0) > 16r90.
  	^machineCodeSize := 11!

Item was changed:
  ----- Method: CogX64Compiler>>concretizeCallFull (in category 'generate machine code') -----
  concretizeCallFull
  	"Since CallFull (and JumpFull) is used to invoke code in dynamically-loaded plugins it shouldn't
  	 assume that code will be loaded within 2Gb of the code zone.  Hence generate a full 64-bit call,
+ 	 movabsq $0x123456789abcdef0, %rax; callq *%rax."
- 	 movabsq 0x123456789abcdef0, %rax; callq *%rax."
  	<inline: true>
  	| operand |
  	operand := operands at: 0.
  	machineCode
  		at: 0 put: 16r48;
+ 		at: 1 put: 16rB8;
- 		at: 1 put: 16rA1;
  		at: 2 put: (operand bitAnd: 16rFF);
  		at: 3 put: (operand >> 8 bitAnd: 16rFF);
  		at: 4 put: (operand >> 16 bitAnd: 16rFF);
  		at: 5 put: (operand >> 24 bitAnd: 16rFF);
  		at: 6 put: (operand >> 32 bitAnd: 16rFF);
  		at: 7 put: (operand >> 40 bitAnd: 16rFF);
  		at: 8 put: (operand >> 48 bitAnd: 16rFF);
  		at: 9 put: (operand >> 56 bitAnd: 16rFF);
  		at: 10 put: 16rFF;
  		at: 11 put: (self mod: ModReg RM: RAX RO: 2).
  	^machineCodeSize := 12!

Item was changed:
  ----- Method: CogX64Compiler>>concretizeJumpFull (in category 'generate machine code') -----
  concretizeJumpFull
  	"Since JumpFull (and CallFull) is used to invoke code in dynamically-loaded plugins it shouldn't
  	 assume that code will be loaded within 2Gb of the code zone.  Hence generate a full 64-bit call,
  	 movabsq 0x123456789abcdef0, %rax; jmpq *%rax."
  	<inline: true>
  	| operand |
  	operand := operands at: 0.
  	machineCode
  		at: 0 put: 16r48;
+ 		at: 1 put: 16rB8;
- 		at: 1 put: 16rA1;
  		at: 2 put: (operand bitAnd: 16rFF);
  		at: 3 put: (operand >> 8 bitAnd: 16rFF);
  		at: 4 put: (operand >> 16 bitAnd: 16rFF);
  		at: 5 put: (operand >> 24 bitAnd: 16rFF);
  		at: 6 put: (operand >> 32 bitAnd: 16rFF);
  		at: 7 put: (operand >> 40 bitAnd: 16rFF);
  		at: 8 put: (operand >> 48 bitAnd: 16rFF);
  		at: 9 put: (operand >> 56 bitAnd: 16rFF);
  		at: 10 put: 16rFF;
  		at: 11 put: (self mod: ModReg RM: RAX RO: 4).
  	^machineCodeSize := 12!

Item was changed:
  ----- Method: Cogit>>handleReadSimulationTrap: (in category 'simulation only') -----
  handleReadSimulationTrap: aProcessorSimulationTrap
- 	"Try to read the value of a variable given its fake address in simulatedVariableGetters.
- 	 simulatedVariableGetters maps to an evaluable that yields the variable's actual value.
- 	 To support the x64, also gracefully accept an address which is in simulatedTrampolines,
- 	 in which case no mapping is necessary."
  	<doNotGenerate>
+ 	| variableValue accessor |
+ 	variableValue := (simulatedVariableGetters at: aProcessorSimulationTrap address) value asInteger.
- 	| address variableValue accessor |
- 	address := aProcessorSimulationTrap address.
- 	variableValue := (simulatedVariableGetters
- 						at: address
- 						ifAbsent:
- 							[(simulatedTrampolines includesKey: address)
- 								ifTrue: [address]
- 								ifFalse: [simulatedVariableGetters errorKeyNotFound: address]]) value asInteger.
  	accessor := aProcessorSimulationTrap registerAccessor.
  	processor
  		perform: accessor
+ 		with: variableValue signedIntToLong.
- 		with: (variableValue == address
- 				ifTrue: [address]
- 				ifFalse: [processor convertIntegerToInternal: variableValue]).
  	accessor ~~ #pc: ifTrue:
  		[processor pc: aProcessorSimulationTrap nextpc]!