[Vm-dev] VM Maker: VMMaker.oscog-eem.1391.mcz
bera.clement at gmail.com
Sun Jun 28 08:14:40 UTC 2015
2015-06-28 5:23 GMT+02:00 Eliot Miranda <eliot.miranda at gmail.com>:
> Hi Clément,
> your code is quite correct. But the old code used two registers and I
> think that using two registers could be faster depending on processor micro
> architecture. So I wrote a version that used two registers if possible.
> Since I doubt it'll make any measurable difference (remote temps are rare
> and the cost of the sequence will be dominated by the reads) I reverted
> back to your original. But the support method might be useful. Sorry fir
> the noise.
Ok I get it.
Anyway I am not pleased with my code because I'd like to rewrite it in a
way where the register for the tempVector can be reused in-between
For example in this kind of code:
| t1 t2 t3 t4 |
[ t1 := t2 := t3 := t4 := 1.
self foo: t1 bar: t2 baz: t3 ] value
I think the tempVect can be stored once in the register and be reused
directly for all the remote temp access.
But I want to implement it such as there is no specific case for tempVector
but a generic case that works for inst vars, temp vectors and maybe more.
Unrelatedly, on ARM processor, I saw that you're not using r12. I would
suggest to use it in register allocation. I have no ARM machine to try but
the idea is:
ExtraRegs := CArrayAccessor on: (Array new: 6).
"Answer an unused abstract register in the liveRegMask."
0 to: self numExtraRegs do:
(cogit register: (ExtraRegs at: i) isInMask: liveRegsMask) ifFalse:
[^ (ExtraRegs at: i) ] ] .
(cogit register: Arg1Reg isInMask: liveRegsMask) ifFalse:
(cogit register: Arg0Reg isInMask: liveRegsMask) ifFalse:
(cogit register: SendNumArgsReg isInMask: liveRegsMask) ifFalse:
(cogit register: ClassReg isInMask: liveRegsMask) ifFalse:
(cogit register: ReceiverResultReg isInMask: liveRegsMask) ifFalse:
CogARMCompiler >>#concreteRegister: registerIndex
[ExtraRegs at: 0] -> [R12].
There might be a few other place, like
#abstractRegisterForConcreteRegister:, but I don't think it's a lot of
Then each instruction using register allocation (and there are quite some
now) would use r12 prior to other regs. This can avoid some spills as the
other regs are sometimes used for trampolines or by convention which is not
the case of R12. In the non sista VM, it may make a difference to have 1
(or maybe 2) extra registers.
What do you think ?
> Eliot (phone)
> On Jun 27, 2015, at 3:25 PM, Clément Bera <bera.clement at gmail.com> wrote:
> I am confused, what did you do in the two last commits ?
> What is example response ?
> Was my code correct ? I tried the simulator only and it worked fine.
> 2015-06-27 21:44 GMT+02:00 <commits at source.squeak.org>:
>> Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
>> ==================== Summary ====================
>> Name: VMMaker.oscog-eem.1391
>> Author: eem
>> Time: 27 June 2015, 12:43:14.39 pm
>> UUID: bdc64a36-203a-4f8f-b8e9-53ef7e41bfb9
>> Ancestors: VMMaker.oscog-eem.1390
>> Revert back to Clément's version of
>> genPushRemoteTempLongBytecode now that
>> example response has been committed.
>> =============== Diff against VMMaker.oscog-eem.1390 ===============
>> Item was changed:
>> ----- Method:
>> StackToRegisterMappingCogit>>genPushRemoteTempLongBytecode (in category
>> 'bytecode generators') -----
>> + | newReg |
>> - | newReg freeReg |
>> newReg := self allocateRegNotConflictingWith: 0.
>> + self MoveMw: (self frameOffsetOfTemporary: byte2) r: FPReg R:
>> - freeReg := self availableRegNotConflictingWith: (self
>> registerMaskFor: newReg).
>> - self MoveMw: (self frameOffsetOfTemporary: byte2) r: FPReg R:
>> (freeReg ifNil: newReg).
>> genLoadSlot: byte1
>> + sourceReg: newReg
>> - sourceReg: (freeReg ifNil: newReg)
>> destReg: newReg.
>> ^self ssPushRegister: newReg!
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