[Vm-dev] VM Maker: VMMaker.oscog-tpr.1126.mcz

commits at source.squeak.org commits at source.squeak.org
Sat Mar 28 02:19:39 UTC 2015


tim Rowledge uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-tpr.1126.mcz

==================== Summary ====================

Name: VMMaker.oscog-tpr.1126
Author: tpr
Time: 27 March 2015, 7:18:08.438 pm
UUID: beeacd84-5c81-496d-b734-2da3371e344e
Ancestors: VMMaker.oscog-eem.1125

Add an improved constant generator that can deal with consts like 0x3FFFF where it can be made fro m0xFFFFFFFF shifted right a few places. This saves several instructions in some important places.

=============== Diff against VMMaker.oscog-eem.1125 ===============

Item was changed:
  CogAbstractInstruction subclass: #CogARMCompiler
  	instanceVariableNames: 'cond'
+ 	classVariableNames: 'AL AddOpcode AndOpcode BICCqR BicOpcode CArg0Reg CArg1Reg CArg2Reg CArg3Reg CC CPSRReg CS CmpOpcode EQ GE GT HI LDMFD LE LR LS LT MI MRS MSR MoveNotOpcode MoveOpcode NE OrOpcode OverflowFlag PC PL R0 R1 R10 R11 R12 R2 R3 R4 R5 R6 R7 R8 R9 RsbOpcode SMLALOpcode SMULL SP STMFD SubOpcode VC VS XorOpcode'
- 	classVariableNames: 'AL AddOpcode AndOpcode BICCqR BicOpcode CArg0Reg CArg1Reg CArg2Reg CArg3Reg CC CPSRReg CS CmpOpcode EQ GE GT HI LDMFD LE LR LS LT MI MRS MSR MoveOpcode NE OrOpcode OverflowFlag PC PL R0 R1 R10 R11 R12 R2 R3 R4 R5 R6 R7 R8 R9 RsbOpcode SMLALOpcode SMULL SP STMFD SubOpcode VC VS XorOpcode'
  	poolDictionaries: ''
  	category: 'VMMaker-JIT'!
  
  !CogARMCompiler commentStamp: 'lw 8/23/2012 19:38' prior: 0!
  I generate ARM instructions from CogAbstractInstructions.  For reference see
  http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.architecture/index.html
  
  The Architecture Reference Manual used is that of version 5, which includes some version 6 instructions. Of those, only pld is used(for PrefetchAw).
  
  This class does not take any special action to flush the instruction cache on instruction-modification.!

Item was changed:
  ----- Method: CogARMCompiler class>>initialize (in category 'class initialization') -----
  initialize
  	
  	"Initialize various ARM instruction-related constants."
  	"CogARMCompiler initialize"
  	
  	| specificOpcodes refs |
  	super initialize.
  	self ~~ CogARMCompiler ifTrue: [^self].
  	
  	R0 := 0.
  	R1 := 1.
  	R2 := 2.
  	R3 := 3.
  	R4 := 4.
  	R5 := 5.
  	R6 := 6.
  	R7 := 7.
  	R8 := 8.
  	R9 := 9.
  	R10 := 10.
  	R11 := 11.
  	R12 := 12..
  	SP := 13..
  	LR := 14.
  	PC := 15.
  	
  	CArg0Reg := 0.
  	CArg1Reg := 1.
  	CArg2Reg := 2.
  	CArg3Reg := 3.
  	
  	RISCTempReg := R10.
  	
  	"Condition Codes. Note that cc=16rF is NOT ALLOWED as a condition; it specifies an extension instruction. See e.g.ARM_ARM v5 DDI01001.pdf A3.2.1"
  	EQ := 0.
  	NE := 1.
  	CS := 2.
  	CC := 3.
  	MI := 4.
  	PL := 5.
  	VS := 6.
  	VC := 7.
  	HI := 8.
  	LS := 9.
  	GE := 10.
  	LT := 11.
  	GT := 12.
  	LE := 13.
  	AL := 14.
  
  	AddOpcode := 	4.
  	AndOpcode := 0.
  	BicOpcode := 14.
  	CmpOpcode := 10.
  	MoveOpcode := 13.
  	OrOpcode := 12.
  	RsbOpcode := 3.
  	SubOpcode := 2.
  	XorOpcode := 1.
  	SMLALOpcode := 7.
+ 	MoveNotOpcode := 15.
  
  	CPSRReg := 16.
  	OverflowFlag := 1 << 28.
  
  	"Specific instructions"
  	LastRTLCode isNil ifTrue:
  		[CogRTLOpcodes initialize].
  	specificOpcodes := #(SMULL MSR MRS LDMFD STMFD BICCqR).
  	refs := (thisContext method literals select: [:l| l isVariableBinding and: [classPool includesKey: l key]]) collect:
  				[:ea| ea key].
  	(classPool keys reject: [:k| (specificOpcodes includes: k) or: [refs includes: k]]) do:
  		[:k|
  		Undeclared declare: k from: classPool].
  	specificOpcodes withIndexDo:
  		[:classVarName :value|
  		self classPool
  			declare: classVarName from: Undeclared;
  			at: classVarName put: value + LastRTLCode - 1]!

Item was added:
+ ----- Method: CogARMCompiler>>ands:rn:rm:lsr: (in category 'ARM convenience instructions') -----
+ ands: destReg rn: srcReg rm: addReg lsr: shft
+ "return an ANDS destReg, srcReg, addReg lsl #shft"
+ "important detail - a 0 shft requires setting the shift-type code to 0 to avoid potential instruction confusion"
+ 	shft = 0
+ 		ifTrue:[^self type: 0 op: AndOpcode set: 1 rn: srcReg rd: destReg shifterOperand: addReg]
+ 		ifFalse:[^self type: 0 op: AndOpcode set: 1 rn: srcReg rd: destReg shifterOperand: ((shft <<7 bitOr: 32) bitOr:  addReg)]!

Item was changed:
  ----- Method: CogARMCompiler>>concretizeAndCqR (in category 'generate machine code - concretize') -----
  concretizeAndCqR
  	"Will get inlined into concretizeAt: switch."
+ 	"AND is very important since it's used to mask all sorts of flags in the jit. We take special care to try to find fast ways to make the masks"
  	<inline: true>
+ 	|val|
+ 	val := operands at: 0.
+ 	self rotateable8bitImmediate: val
- 	self rotateable8bitImmediate: (operands at: 0)
  		ifTrue: [ :rot :immediate | | reg |
  			reg := self concreteRegister: (operands at: 1).
  			self machineCodeAt: 0 put: (self ands: reg rn: reg imm: immediate ror: rot).
  			^machineCodeSize := 4]
  		ifFalse: [
  			"see if the constant bit-inverted makes a quick value and if so BIC it instead
  			If the value is -ve, we 2s complement it instead"
+ 			|invVal|
+ 			val <0
+ 				ifTrue:[invVal := -1 - val]
+ 				ifFalse:[invVal := val bitInvert32].
+ 			self rotateable8bitImmediate: invVal
- 			|val|
- 			val := operands at: 0.
- 			val <0 ifTrue:[val := -1 - val] ifFalse:[val := val bitInvert32].
- 			self rotateable8bitImmediate: val
  				ifTrue: [ :rot :immediate | |reg|
  					reg := self concreteRegister: (operands at: 1).
  					self machineCodeAt: 0 put: (self bics: reg rn: reg imm: immediate ror: rot).
  					^machineCodeSize := 4]
+ 				ifFalse: ["let's try to see if the constant can be made from a simple shift of 0xFFFFFFFF"
+ 					|hb reg|
+ 					reg := self concreteRegister: (operands at: 1).
+ 					hb := (operands at: 0) highBit.
+ 					1 << hb = (val +1)
+ 						ifTrue: [ "MVN temp reg, 0, making 0xffffffff"
+ 							self machineCodeAt: 0 put:(self mvn: RISCTempReg imm: 0 ror: 0).
+ 							"Then AND reg, temp reg, lsr #(32-hb)"
+ 							 self machineCodeAt: 4 put:(self ands: reg rn: reg rm: RISCTempReg lsr: (32-hb )).
+ 							^machineCodeSize :=8]
+ 						ifFalse: [^self concretizeDataOperationCwR: AndOpcode]]]!
- 				ifFalse: [^self concretizeDataOperationCwR: 0]]!

Item was added:
+ ----- Method: CogARMCompiler>>mvn:imm:ror: (in category 'ARM convenience instructions') -----
+ mvn: destReg imm: immediate8bitValue ror: rot
+ 	"Remember the ROR is doubled by the cpu so use 30>>1 etc.
+ 	MVN destReg, #immediate8BitValue ROR rot"
+ 	^self type: 1 op: MoveNotOpcode set: 0 rn: 0 rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate8bitValue)!



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