[Vm-dev] VM Maker: Cog-eem.255.mcz

[commits at source.squeak.org]

Eliot Miranda uploaded a new version of Cog to project VM Maker:
http://source.squeak.org/VMMaker/Cog-eem.255.mcz

==================== Summary ====================

Name: Cog-eem.255
Author: eem
Time: 28 March 2015, 1:30:14.558 pm
UUID: 87ca5f19-8aeb-4c97-b111-3d67ea88e11a
Ancestors: Cog-eem.254

Include the offset in the relevant addressing modes
in load and store exceptions in the ARM alien.

=============== Diff against Cog-eem.254 ===============

Item was changed:
  ----- Method: GdbARMAlien>>handleFailingLoadStore:at: (in category 'error handling') -----
  handleFailingLoadStore: instr at: pc
+ 	| baseReg destReg srcReg offset |
- 	| baseReg destReg srcReg |
  	baseReg := self registerStateGetters at: (instr >> 16 bitAnd: 15)+ 1.
  	destReg := self registerStateSetters at: (instr >> 12 bitAnd: 15) + 1.
  	srcReg := self registerStateGetters at: (instr >> 12 bitAnd: 15) + 1.
+ 	"See e.g. A5.2.2/A5-20 ARM ARM v6"
+ 	offset := (instr >> 21 bitAnd: 2r1111001) = 2r0101000
+ 				ifTrue:
+ 					[(instr >> 23 anyMask: 1) "U bit"
+ 						ifTrue: [instr bitAnd: 16rFFF]
+ 						ifFalse: [(instr bitAnd: 16rFFF) negated]]
+ 				ifFalse:
+ 					[0].
  	(self instructionIsLDR: instr) ifTrue:
  		[^(ProcessorSimulationTrap
  				pc: pc
  				nextpc: pc + 4 
+ 				address: (self perform: baseReg) + offset
- 				address: (self perform: baseReg)
  				type: #read
  				accessor: destReg)
  			signal].
  	(self instructionIsSTR: instr) ifTrue:
  		[^(ProcessorSimulationTrap
  				pc: pc
  				nextpc: pc + 4 
+ 				address: (self perform: baseReg) + offset
- 				address: (self perform: baseReg)
  				type: #write
  				accessor: srcReg)
  			signal].
  	"Lars handled byte read/write failures.  i don't think we need to"
  	"(self instructionIsLDRB: instr) ifTrue:
  		[??].
  	(self instructionIsSTRB: instr) ifTrue:
  		[??]."
  	self error: 'handleFailingLoadStore:at: invoked for non-load/store?'!