[Vm-dev] Re: ARM Cog progress

[Nicolas Cellier]

2015-05-21 19:42 GMT+02:00 tim Rowledge <tim at rowledge.org>:

>
>
> On 21-05-2015, at 10:19 AM, Eliot Miranda <eliot.miranda at gmail.com> wrote:
> >>
> >> Four 32-bit instructions loading 16-bit pieces, or one pc-relative load.
> >
> > So out-of-line = 12 bytes vs in-line = 16 bytes.  For me, given that ARM
> has always supported out-of-line, and it should have good performance, I'd
> go for out-of-line.  But it's performance could be much worse.  Anyone have
> any numbers?
>
> Also no absolute need to do 64bit oops with AArch64. It will be quite
> happy to do 32 bit oops. So 2x 16bit chunks would be fine for both that and
> v7. So far as I can work out all the operations can work in 32bit
> quantities, even rotations/shifts/compare.
>
> And there is the hilarious concept of conditional comparisons - if the
> condition flags match a vector of condition flags, then do a compare of
> some sort and if that is true, set the flags as appropriate, otherwise set
> the flags to another vector. I’d love to see the logic that persuaded them
> to do that.
>
> I swear I spotted a WTF instruction in there somewhere.
>
>
Also a ROTFL
I think it just matches the conversion from SmallDouble to native double
that Eliot naivly coded with many more instructions.

tim
> --
> tim Rowledge; tim at rowledge.org; http://www.rowledge.org/tim
> State-of-the-art: What we could do with enough money.
>
>
>
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