[Vm-dev] VM Maker: VMMaker.oscog-eem.1529.mcz
commits at source.squeak.org
commits at source.squeak.org
Sun Nov 22 18:31:25 UTC 2015
Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1529.mcz
==================== Summary ====================
Name: VMMaker.oscog-eem.1529
Author: eem
Time: 22 November 2015, 10:29:01.889 am
UUID: 6b91882c-e59c-4c22-8d16-77d16299d2d4
Ancestors: VMMaker.oscog-eem.1528
Fix generation of the CPIC prototype for inline literals x64.
Add some more opcodes to handle compare/branch collapse for CmpCqR on MIPSEL.
=============== Diff against VMMaker.oscog-eem.1528 ===============
Item was added:
+ ----- Method: CogAbstractInstruction>>storeLiteral32:beforeFollowingAddress: (in category 'inline cacheing') -----
+ storeLiteral32: literal32 beforeFollowingAddress: followingAddress
+ "Answer the constant loaded by the instruction sequence just before this address:"
+ <inline: true>
+ ^objectMemory wordSize = 8
+ ifTrue: [self subclassResponsibility]
+ ifFalse: [self storeLiteral: literal32 beforeFollowingAddress: followingAddress]!
Item was removed:
- ----- Method: CogInLineLiteralsX64Compiler>>abstractRegisterForConcreteRegister: (in category 'private') -----
- abstractRegisterForConcreteRegister: reg
- (self concreteRegister: TempReg) = reg ifTrue: [^TempReg].
- (self concreteRegister: ReceiverResultReg) = reg ifTrue: [^ReceiverResultReg].
- (self concreteRegister: ClassReg) = reg ifTrue: [^ClassReg].
- (self concreteRegister: SendNumArgsReg) = reg ifTrue: [^SendNumArgsReg].
- (self concreteRegister: Arg0Reg) = reg ifTrue: [^Arg0Reg].
- (self concreteRegister: Arg1Reg) = reg ifTrue: [^Arg1Reg].
- (self concreteRegister: FPReg) = reg ifTrue: [^FPReg].
- (self concreteRegister: SPReg) = reg ifTrue: [^SPReg].
- (self concreteRegister: RISCTempReg) = reg ifTrue: [^RISCTempReg].
- (self concreteRegister: VarBaseReg) = reg ifTrue: [^VarBaseReg].
- (self concreteRegister: Scratch0Reg) = reg ifTrue: [^Scratch0Reg].
- (self concreteRegister: Scratch1Reg) = reg ifTrue: [^Scratch1Reg].
- (self concreteRegister: Scratch2Reg) = reg ifTrue: [^Scratch2Reg].
- (self concreteRegister: Scratch3Reg) = reg ifTrue: [^Scratch3Reg].
- (self concreteRegister: Scratch4Reg) = reg ifTrue: [^Scratch4Reg].
- (self concreteRegister: Scratch5Reg) = reg ifTrue: [^Scratch5Reg].
- self error: 'could not find abstract register'.
- ^0
-
- "({ TempReg. ReceiverResultReg. ClassReg. SendNumArgsReg. Arg0Reg. Arg1Reg.
- FPReg. SPReg.
- RISCTempReg. VarBaseReg.
- Scratch0Reg. Scratch1Reg. Scratch2Reg. Scratch3Reg. Scratch4Reg. Scratch5Reg. } collect: [:i| self basicNew concreteRegister: i]) sort"
-
- "While the below works fine in Smalltalk it of course doesn't work in C ;)"
-
- "^reg caseOf: {
- [self concreteRegister: TempReg] -> [TempReg].
- [self concreteRegister: ReceiverResultReg] -> [ReceiverResultReg].
- [self concreteRegister: ClassReg] -> [ClassReg].
- [self concreteRegister: SendNumArgsReg] -> [SendNumArgsReg].
- [self concreteRegister: Arg0Reg] -> [Arg0Reg].
- [self concreteRegister: Arg1Reg] -> [Arg1Reg].
- [self concreteRegister: FPReg] -> [FPReg].
- [self concreteRegister: SPReg] -> [SPReg] }"!
Item was changed:
CogAbstractInstruction subclass: #CogMIPSELCompiler
instanceVariableNames: ''
+ classVariableNames: 'AddCheckOverflowCqR AddCheckOverflowRR BrEqCqR BrEqRR BrGtzRR BrLezRR BrNeCqR BrNeRR Cmp CmpSGT CmpSLT CmpUGT CmpULT ConcreteVarBaseReg MulCheckOverflowRR MulRR Overflow OverflowTemp1 OverflowTemp2 SubCheckOverflowCqR SubCheckOverflowRR TargetReg'
- classVariableNames: 'AddCheckOverflowCqR AddCheckOverflowRR BrEqRR BrGtzRR BrLezRR BrNeRR Cmp CmpSGT CmpSLT CmpUGT CmpULT ConcreteVarBaseReg MulCheckOverflowRR MulRR Overflow OverflowTemp1 OverflowTemp2 SubCheckOverflowCqR SubCheckOverflowRR TargetReg'
poolDictionaries: 'MIPSConstants'
category: 'VMMaker-JIT'!
Item was changed:
----- Method: CogMIPSELCompiler class>>initialize (in category 'class initialization') -----
initialize
"CogMIPSELCompiler initialize"
super initialize.
ConcreteVarBaseReg := S6.
"Simulating a condition register."
Cmp := T0.
CmpSLT := T1.
CmpSGT := T2.
CmpULT := T3.
CmpUGT := T4.
Overflow := T0.
OverflowTemp1 := T1.
OverflowTemp2 := T2.
"OABI position independent code expects T9 to have its entry point on entry?"
self flag: #OABI.
TargetReg := T9.
"Specific instructions"
self
initializeSpecificOpcodes: #(MulRR
AddCheckOverflowCqR AddCheckOverflowRR MulCheckOverflowRR SubCheckOverflowCqR SubCheckOverflowRR
"Ryan, here are proposed opcodes for conditional branches."
+ BrEqRR BrNeRR BrLezRR BrGtzRR BrEqCqR BrNeCqR)
+ in: thisContext method!
- BrEqRR BrNeRR BrLezRR BrGtzRR)
- in: thisContext method
-
- !
Item was changed:
----- Method: CogMIPSELCompiler>>noteFollowingConditionalBranch: (in category 'abstract instructions') -----
noteFollowingConditionalBranch: branch
"Support for processors without condition codes, such as the MIPS.
Answer the branch opcode. Modify the receiver and the branch to
implement a suitable conditional branch that doesn't depend on
condition codes being set by the receiver."
<var: #branch type: #'AbstractInstruction *'>
branch opcode caseOf: {
[JumpOverflow] -> [opcode := opcode caseOf: {
[AddCqR] -> [AddCheckOverflowCqR].
[AddRR] -> [AddCheckOverflowRR].
[MulRR] -> [MulCheckOverflowRR].
[SubCqR] -> [SubCheckOverflowCqR].
[SubRR] -> [SubCheckOverflowRR].
}].
[JumpNoOverflow] -> [opcode := opcode caseOf: {
[AddCqR] -> [AddCheckOverflowCqR].
[AddRR] -> [AddCheckOverflowRR].
[MulRR] -> [MulCheckOverflowRR].
[SubCqR] -> [SubCheckOverflowCqR].
[SubRR] -> [SubCheckOverflowRR].
}].
"Ryan, I'm imagining that all the other cases go in here, such as collapsing CmpRR; JumpZero to Label; BrEqRR.
This is obviously not nearly complete."
[JumpZero] -> [opcode caseOf: {
[CmpRR] -> [branch setOpcode: BrEqRR andOperandsFrom: self.
+ branch operands at: 2 put: (operands at: 1).
- branch operands at: 3 put: (operands at: 1).
opcode := Label].
}].
[JumpNonZero] -> [opcode caseOf: {
[CmpRR] -> [branch setOpcode: BrNeRR andOperandsFrom: self.
+ branch operands at: 2 put: (operands at: 1).
- branch operands at: 3 put: (operands at: 1).
opcode := Label].
+ [CmpCqR] -> [branch setOpcode: BrNeCqR andOperandsFrom: self.
+ branch operands at: 2 put: (operands at: 1).
+ opcode := Label].
}].
[JumpLongZero] -> [opcode caseOf: {
[CmpRR] -> [branch setOpcode: BrNeRR andOperandsFrom: self.
"skip the following long branch"
+ branch operands at: 2 put: self jumpLongByteSize.
- branch operands at: 3 put: self jumpLongByteSize.
opcode := JumpLong].
+ [CmpCqR] -> [branch setOpcode: BrNeCqR andOperandsFrom: self.
+ "skip the following long branch"
+ branch operands at: 2 put: self jumpLongByteSize.
+ opcode := JumpLong].
}].
[JumpLongNonZero] -> [opcode caseOf: {
[CmpRR] -> [branch setOpcode: BrEqRR andOperandsFrom: self.
"skip the following long branch"
+ branch operands at: 2 put: self jumpLongByteSize.
- branch operands at: 3 put: self jumpLongByteSize.
opcode := JumpLong].
}].
}
"No otherwise for now to catch all cases"
"otherwise: []".
^branch!
Item was changed:
----- Method: CogMIPSELCompiler>>setOpcode:andOperandsFrom: (in category 'accessing') -----
setOpcode: anOpcode andOperandsFrom: cmpInstruction
<var: #cmpInstruction type: #'AbstractInstruction *'>
<inline: true>
opcode := anOpcode.
operands
+ at: 0 put: (cmpInstruction operands at: 0);
+ at: 1 put: (cmpInstruction operands at: 1)!
- at: 0 put: (cmpInstruction opcodes at: 0);
- at: 1 put: (cmpInstruction opcodes at: 1)!
Item was added:
+ ----- Method: CogX64Compiler>>abstractRegisterForConcreteRegister: (in category 'private') -----
+ abstractRegisterForConcreteRegister: reg
+ (self concreteRegister: TempReg) = reg ifTrue: [^TempReg].
+ (self concreteRegister: ReceiverResultReg) = reg ifTrue: [^ReceiverResultReg].
+ (self concreteRegister: ClassReg) = reg ifTrue: [^ClassReg].
+ (self concreteRegister: SendNumArgsReg) = reg ifTrue: [^SendNumArgsReg].
+ (self concreteRegister: Arg0Reg) = reg ifTrue: [^Arg0Reg].
+ (self concreteRegister: Arg1Reg) = reg ifTrue: [^Arg1Reg].
+ (self concreteRegister: FPReg) = reg ifTrue: [^FPReg].
+ (self concreteRegister: SPReg) = reg ifTrue: [^SPReg].
+ (self concreteRegister: RISCTempReg) = reg ifTrue: [^RISCTempReg].
+ (self concreteRegister: VarBaseReg) = reg ifTrue: [^VarBaseReg].
+ (self concreteRegister: Scratch0Reg) = reg ifTrue: [^Scratch0Reg].
+ (self concreteRegister: Scratch1Reg) = reg ifTrue: [^Scratch1Reg].
+ (self concreteRegister: Scratch2Reg) = reg ifTrue: [^Scratch2Reg].
+ (self concreteRegister: Scratch3Reg) = reg ifTrue: [^Scratch3Reg].
+ (self concreteRegister: Scratch4Reg) = reg ifTrue: [^Scratch4Reg].
+ (self concreteRegister: Scratch5Reg) = reg ifTrue: [^Scratch5Reg].
+ self error: 'could not find abstract register'.
+ ^0
+
+ "({ TempReg. ReceiverResultReg. ClassReg. SendNumArgsReg. Arg0Reg. Arg1Reg.
+ FPReg. SPReg.
+ RISCTempReg. VarBaseReg.
+ Scratch0Reg. Scratch1Reg. Scratch2Reg. Scratch3Reg. Scratch4Reg. Scratch5Reg. } collect: [:i| self basicNew concreteRegister: i]) sort"
+
+ "While the below works fine in Smalltalk it of course doesn't work in C ;)"
+
+ "^reg caseOf: {
+ [self concreteRegister: TempReg] -> [TempReg].
+ [self concreteRegister: ReceiverResultReg] -> [ReceiverResultReg].
+ [self concreteRegister: ClassReg] -> [ClassReg].
+ [self concreteRegister: SendNumArgsReg] -> [SendNumArgsReg].
+ [self concreteRegister: Arg0Reg] -> [Arg0Reg].
+ [self concreteRegister: Arg1Reg] -> [Arg1Reg].
+ [self concreteRegister: FPReg] -> [FPReg].
+ [self concreteRegister: SPReg] -> [SPReg] }"!
Item was changed:
----- Method: CogX64Compiler>>computeMaximumSize (in category 'generate machine code') -----
(excessive size, no diff calculated)
Item was added:
+ ----- Method: CogX64Compiler>>storeLiteral32:beforeFollowingAddress: (in category 'inline cacheing') -----
+ storeLiteral32: literal beforeFollowingAddress: followingAddress
+ "Rewrite the 32-bit literal in the instruction immediately preceding followingAddress."
+ objectMemory
+ byteAt: followingAddress - 1 put: (literal >> 24 bitAnd: 16rFF);
+ byteAt: followingAddress - 2 put: (literal >> 16 bitAnd: 16rFF);
+ byteAt: followingAddress - 3 put: (literal >> 8 bitAnd: 16rFF);
+ byteAt: followingAddress - 4 put: (literal bitAnd: 16rFF)!
Item was changed:
----- Method: Cogit>>expectedClosedPICPrototype: (in category 'in-line cacheing') -----
expectedClosedPICPrototype: cPIC
"Answer 0 if the ClosedPIC is as expected from compileClosedPICPrototype,
otherwise answer an error code identifying the first discrepancy found."
"self disassembleFrom: methodZoneBase + (self sizeof: CogMethod) to: methodZoneBase + closedPICSize"
<var: #cPIC type: #'CogMethod *'>
| pc object entryPoint |
pc := cPIC asUnsignedInteger + firstCPICCaseOffset.
"First jump is unconditional; subsequent ones are conditional"
object := backEnd literalBeforeFollowingAddress: pc - backEnd jumpLongByteSize.
self assert: object = 16r5EAF00D.
entryPoint := backEnd jumpLongTargetBeforeFollowingAddress: pc.
self assert: entryPoint = (self cPICPrototypeCaseOffset + 16rCA5E10).
1 to: maxCPICCases - 1 do:
[:i | | methodObjPC classTagPC |
pc := pc + cPICCaseSize.
methodObjPC := pc - backEnd jumpLongConditionalByteSize - backEnd cmpC32RTempByteSize.
object := backEnd literalBeforeFollowingAddress: methodObjPC.
self assert: object = (16rBADA550 + i).
backEnd storeLiteral: (object bitXor: 16rA5A5A5A5) beforeFollowingAddress: methodObjPC.
object := backEnd literalBeforeFollowingAddress: methodObjPC.
self assert: object = (16rBADA550 + i bitXor: 16rA5A5A5A5).
backEnd storeLiteral: (object bitXor: 16rA5A5A5A5) beforeFollowingAddress: methodObjPC.
classTagPC := pc - backEnd jumpLongConditionalByteSize.
object := backEnd literal32BeforeFollowingAddress: classTagPC.
self assert: object = (16rBABE1F15 + i).
+ backEnd storeLiteral32: (object bitXor: 16r5A5A5A5A) beforeFollowingAddress: classTagPC.
- backEnd storeLiteral: (object bitXor: 16r5A5A5A5A) beforeFollowingAddress: classTagPC.
object := backEnd literal32BeforeFollowingAddress: classTagPC.
self assert: object = (16rBABE1F15 + i bitXor: 16r5A5A5A5A).
+ backEnd storeLiteral32: (object bitXor: 16r5A5A5A5A) beforeFollowingAddress: classTagPC.
- backEnd storeLiteral: (object bitXor: 16r5A5A5A5A) beforeFollowingAddress: classTagPC.
entryPoint := backEnd jumpLongConditionalTargetBeforeFollowingAddress: pc.
self assert: entryPoint = (self cPICPrototypeCaseOffset + 16rCA5E10 + (i * 16))].
entryPoint := backEnd jumpLongTargetBeforeFollowingAddress: pc + cPICEndSize - literalsManager endSizeOffset.
self assert: entryPoint = (self cPICMissTrampolineFor: 0).
^0!
Item was removed:
- ----- Method: Cogit>>storeClassRef:inClosedPICAt: (in category 'in-line cacheing') -----
- storeClassRef: classObj inClosedPICAt: address
- <var: #address type: #usqInt>
- <inline: true>
- "If inline cache tags are not objects they will be 32-bit values."
- objectRepresentation inlineCacheTagsMayBeObjects
- ifTrue: [backEnd storeLiteral: classObj beforeFollowingAddress: address]
- ifFalse: [backEnd storeLiteral32: classObj beforeFollowingAddress: address]!
More information about the Vm-dev
mailing list