[Vm-dev] VM Maker: VMMaker.oscog-eem.1477.mcz

commits at source.squeak.org commits at source.squeak.org
Tue Sep 29 01:48:02 UTC 2015


Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1477.mcz

==================== Summary ====================

Name: VMMaker.oscog-eem.1477
Author: eem
Time: 28 September 2015, 6:46:16.264 pm
UUID: 108eaaea-883b-4418-9167-b10697ae9f7e
Ancestors: VMMaker.oscog-eem.1476

x64 Cogit:
Fix PushCw, and fix the tests so they're not confused by the scratch value left behind in RISCTempReg.  Fix fetch/storeLiteral[:]beforeFollowingAddress: for PushCw.
Fix slip in concretizeMoveCqR

=============== Diff against VMMaker.oscog-eem.1476 ===============

Item was changed:
  ----- Method: AbstractInstructionTests>>runAddCwR: (in category 'running') -----
  runAddCwR: assertPrintBar
  	"self defaultTester runAddCwR: false"
  	| memory |
  	memory := ByteArray new: self concreteCompilerClass new machineCodeBytes.
  	self concreteCompilerClass dataRegistersWithAccessorsDo:
  		[:reg :rgetter :rsetter|
  		self pairs: (-2 to: 2)  do:
  			[:a :b| | inst len bogus |
  			inst := self gen: AddCwR operand: a operand: reg.
  			len := inst concretizeAt: 0.
  			memory replaceFrom: 1 to: len with: inst machineCode object startingAt: 1.
  			self processor
  				reset;
+ 				perform: rsetter with: (self processor convertIntegerToInternal: b).
- 				perform: rsetter with: b signedIntToLong.
  			[[processor pc < len] whileTrue:
  				[self processor singleStepIn: memory]]
  				on: Error
  				do: [:ex| ].
  			"self processor printRegistersOn: Transcript.
  			 Transcript show: (self processor disassembleInstructionAt: 0 In: memory); cr"
  			assertPrintBar
  				ifTrue: [self assert: processor pc = inst machineCodeSize.
  						self assertCheckLongArithOpCodeSize: inst machineCodeSize]
  				ifFalse: [bogus := processor pc ~= inst machineCodeSize].
  			self concreteCompilerClass dataRegistersWithAccessorsDo:
  				[:ireg :getter :setter| | expected |
+ 				(self concreteCompilerClass isConcreteRISCTempRegister: ireg) ifFalse:
+ 					[expected := getter == rgetter ifTrue: [b + a] ifFalse: [0].
+ 					assertPrintBar
+ 						ifTrue: [self assert: (self processor convertInternalToInteger: (self processor perform: getter)) equals: expected]
+ 						ifFalse:
+ 							[(self processor convertInternalToInteger: (self processor perform: getter)) ~= expected ifTrue:
+ 								[bogus := true]]].
+ 					assertPrintBar ifFalse:
+ 						[Transcript
+ 							nextPutAll: rgetter; nextPut: $(; print: b; nextPutAll: ') + '; print: a; nextPutAll: ' = ';
+ 							print: (self processor convertInternalToInteger: (self processor perform: rgetter)); cr; flush.
+ 						 bogus ifTrue:
+ 							[self processor printRegistersOn: Transcript.
+ 							 Transcript show: (self processor disassembleInstructionAt: 0 In: memory); cr]]]]]!
- 				expected := getter == rgetter ifTrue: [a + b] ifFalse: [0].
- 				assertPrintBar
- 					ifTrue: [self assert: (self processor perform: getter) signedIntFromLong = expected]
- 					ifFalse:
- 						[(self processor perform: getter) signedIntFromLong ~= expected ifTrue:
- 							[bogus := true]]].
- 				assertPrintBar ifFalse:
- 					[Transcript
- 						nextPutAll: rgetter; nextPut: $(; print: b; nextPutAll: ') + '; print: a; nextPutAll: ' = ';
- 						print: (self processor perform: rgetter) signedIntFromLong; cr; flush.
- 					 bogus ifTrue:
- 						[self processor printRegistersOn: Transcript.
- 						 Transcript show: (self processor disassembleInstructionAt: 0 In: memory); cr]]]]!

Item was changed:
  ----- Method: AbstractInstructionTests>>runSubCwR: (in category 'running') -----
  runSubCwR: assertPrintBar
  	"self defaultTester runSubCwR: false"
  	| memory |
  	memory := ByteArray new: self concreteCompilerClass new machineCodeBytes.
  	self concreteCompilerClass dataRegistersWithAccessorsDo:
  		[:reg :rgetter :rsetter|
  		self pairs: (-2 to: 2)  do:
  			[:a :b| | inst len bogus |
  			inst := self gen: SubCwR operand: a operand: reg.
  			len := inst concretizeAt: 0.
  			memory replaceFrom: 1 to: len with: inst machineCode object startingAt: 1.
  			self processor
  				reset;
+ 				perform: rsetter with: (self processor convertIntegerToInternal: b).
- 				perform: rsetter with: b signedIntToLong.
  			[[processor pc < len] whileTrue:
  				[self processor singleStepIn: memory]]
  				on: Error
  				do: [:ex| ].
  			"self processor printRegistersOn: Transcript.
  			 Transcript show: (self processor disassembleInstructionAt: 0 In: memory); cr"
  			assertPrintBar
  				ifTrue: [self assert: processor pc = inst machineCodeSize.
  						self assertCheckLongArithOpCodeSize: inst machineCodeSize]
  				ifFalse: [bogus := processor pc ~= inst machineCodeSize].
  			self concreteCompilerClass dataRegistersWithAccessorsDo:
  				[:ireg :getter :setter| | expected |
+ 				(self concreteCompilerClass isConcreteRISCTempRegister: ireg) ifFalse:
+ 					[expected := getter == rgetter ifTrue: [b - a] ifFalse: [0].
+ 					assertPrintBar
+ 						ifTrue: [self assert: (self processor convertInternalToInteger: (self processor perform: getter)) equals: expected]
+ 						ifFalse:
+ 							[(self processor convertInternalToInteger: (self processor perform: getter)) ~= expected ifTrue:
+ 								[bogus := true]]].
+ 					assertPrintBar ifFalse:
+ 						[Transcript
+ 							nextPutAll: rgetter; nextPut: $(; print: b; nextPutAll: ') - '; print: a; nextPutAll: ' = ';
+ 							print: (self processor convertInternalToInteger: (self processor perform: rgetter)); cr; flush.
+ 						 bogus ifTrue:
+ 							[self processor printRegistersOn: Transcript.
+ 							 Transcript show: (self processor disassembleInstructionAt: 0 In: memory); cr]]]]]!
- 				expected := getter == rgetter ifTrue: [b - a] ifFalse: [0].
- 				assertPrintBar
- 					ifTrue: [self assert: (self processor perform: getter) signedIntFromLong = expected]
- 					ifFalse:
- 						[(self processor perform: getter) signedIntFromLong ~= expected ifTrue:
- 							[bogus := true]]].
- 				assertPrintBar ifFalse:
- 					[Transcript
- 						nextPutAll: rgetter; nextPut: $(; print: b; nextPutAll: ') - '; print: a; nextPutAll: ' = ';
- 						print: (self processor perform: rgetter) signedIntFromLong; cr; flush.
- 					 bogus ifTrue:
- 						[self processor printRegistersOn: Transcript.
- 						 Transcript show: (self processor disassembleInstructionAt: 0 In: memory); cr]]]]!

Item was added:
+ ----- Method: CogARMCompiler class>>isConcreteRISCTempRegister: (in category 'testing') -----
+ isConcreteRISCTempRegister: concreteRegister
+ 	"For tests to filter-out bogus values left in the ConcreteRISCTempRegister, if any."
+ 	^concreteRegister = ConcreteIPReg!

Item was added:
+ ----- Method: CogAbstractInstruction class>>isConcreteRISCTempRegister: (in category 'testing') -----
+ isConcreteRISCTempRegister: concreteRegister
+ 	"For tests to filter-out bogus values left in the ConcreteRISCTempRegister, if any."
+ 	^self subclassResponsibility!

Item was added:
+ ----- Method: CogIA32Compiler class>>isConcreteRISCTempRegister: (in category 'testing') -----
+ isConcreteRISCTempRegister: concreteRegister
+ 	"For tests to filter-out bogus values left in the ConcreteRISCTempRegister, if any."
+ 	^false!

Item was changed:
  CogX64Compiler subclass: #CogInLineLiteralsX64Compiler
  	instanceVariableNames: ''
+ 	classVariableNames: 'ConcreteRISCTempReg'
- 	classVariableNames: ''
  	poolDictionaries: ''
  	category: 'VMMaker-JIT'!

Item was added:
+ ----- Method: CogInLineLiteralsX64Compiler class>>initialize (in category 'class initialization') -----
+ initialize
+ 	ConcreteRISCTempReg := self basicNew concreteRegister: RISCTempReg!

Item was added:
+ ----- Method: CogInLineLiteralsX64Compiler class>>isConcreteRISCTempRegister: (in category 'testing') -----
+ isConcreteRISCTempRegister: concreteRegister
+ 	"For tests to filter-out bogus values left in the ConcreteRISCTempRegister, if any."
+ 	^concreteRegister = ConcreteRISCTempReg!

Item was changed:
  ----- Method: CogInLineLiteralsX64Compiler>>concretizeArithCwR: (in category 'generate machine code') -----
  concretizeArithCwR: opcode
  	| value reg |
  	value := operands at: 0.
  	reg := self concreteRegister: (operands at: 1).
  	machineCode
+ 		at:  0 put: (self rexR: ConcreteRISCTempReg x: 0 b: ConcreteRISCTempReg);
+ 		at:  1 put: 16rB8 + (ConcreteRISCTempReg bitAnd: 7);
- 		at:  0 put: (self rexR: RISCTempReg x: 0 b: RISCTempReg);
- 		at:  1 put: 16rB8 + (RISCTempReg bitAnd: 7);
  		at:  2 put: (value bitAnd: 16rFF);
  		at:  3 put: (value >> 8 bitAnd: 16rFF);
  		at:  4 put: (value >> 16 bitAnd: 16rFF);
  		at:  5 put: (value >> 24 bitAnd: 16rFF);
  		at:  6 put: (value >> 32 bitAnd: 16rFF);
  		at:  7 put: (value >> 40 bitAnd: 16rFF);
  		at:  8 put: (value >> 48 bitAnd: 16rFF);
  		at:  9 put: (value >> 56 bitAnd: 16rFF);
+ 		at: 10 put: (self rexR: reg x: 0 b: ConcreteRISCTempReg);
- 		at: 10 put: (self rexR: RISCTempReg x: 0 b: reg);
  		at: 11 put: opcode;
+ 		at: 12 put: (self mod: ModReg RM: ConcreteRISCTempReg RO: reg).
- 		at: 12 put: (self mod: ModReg RM: reg RO: RISCTempReg).
  	^machineCodeSize := 13!

Item was changed:
  ----- Method: CogInLineLiteralsX64Compiler>>concretizePushCw (in category 'generate machine code') -----
  concretizePushCw
  	"Will get inlined into concretizeAt: switch."
  	<inline: true>
  	| value |
  	value := operands at: 0.
  	machineCode
+ 		at:  0 put: (self rexR: ConcreteRISCTempReg x: 0 b: ConcreteRISCTempReg);
+ 		at:  1 put: 16rB8 + (ConcreteRISCTempReg bitAnd: 7);
+ 		at:  2 put: (value bitAnd: 16rFF);
+ 		at:  3 put: (value >> 8 bitAnd: 16rFF);
+ 		at:  4 put: (value >> 16 bitAnd: 16rFF);
+ 		at:  5 put: (value >> 24 bitAnd: 16rFF);
+ 		at:  6 put: (value >> 32 bitAnd: 16rFF);
+ 		at:  7 put: (value >> 40 bitAnd: 16rFF);
+ 		at:  8 put: (value >> 48 bitAnd: 16rFF);
+ 		at:  9 put: (value >> 56 bitAnd: 16rFF);
+ 		at: 10 put: 16r41;
+ 		at: 11 put: 16r50 + (ConcreteRISCTempReg - 8). "The 50 will disambiguate between MoveCwR, PushCwR and ArithCwR, which ends with a (self mod: ModReg RM: 0 RO: 0)"
+ 		self assert: ConcreteRISCTempReg >= 8.
+ 	self assert: (self mod: ModReg RM: 0 RO: 0) > 16r57.
+ 	^machineCodeSize := 12!
- 		at: 0 put: 16r68;
- 		at: 1 put: (value >> 8 bitAnd: 16rFF);
- 		at: 2 put: (value >> 16 bitAnd: 16rFF);
- 		at: 3 put: (value >> 24 bitAnd: 16rFF);
- 		at: 4 put: (value >> 32 bitAnd: 16rFF);
- 		at: 5 put: (value >> 40 bitAnd: 16rFF);
- 		at: 6 put: (value >> 48 bitAnd: 16rFF);
- 		at: 7 put: (value >> 56 bitAnd: 16rFF);
- 		at: 8 put: 16r90. "Add a nop to disambiguate between MoveCwR/PushCwR and ArithCwR, which ends with a (self mod: ModReg RM: 0 RO: 0)"
- 	self assert: (self mod: ModReg RM: 0 RO: 0) > 16r90.
- 	^machineCodeSize := 9!

Item was changed:
  ----- Method: CogInLineLiteralsX64Compiler>>literalBeforeFollowingAddress: (in category 'inline cacheing') -----
  literalBeforeFollowingAddress: followingAddress
+ 	"Answer the literal embedded in the instruction immediately preceding followingAddress.
+ 	 This is used in the MoveCwR, PushCwR and CmpCwR cases; these are distinguished by a
+ 	 nop following the literal load in MoveCwR, a 16r50 + reg ending the PushCwR sequence, and
+ 	 a (self mod: ModReg RM: rX RO: rY) ending the CmpCwR sequence, which is at least 16rC0."
+ 	| lastByte base |
+ 	lastByte := objectMemory byteAt: followingAddress - 1.
+ 	base := followingAddress - (lastByte <= 16r90
+ 									ifTrue:
+ 										[lastByte = 16r90
+ 											ifTrue: [9]		"MoveCwR"
+ 											ifFalse: [10]]	"PushCwR"
+ 									ifFalse: [11]).			"ArithCwR"
- 	"Answer the literal embedded in the instruction immediately preceeding followingAddress.
- 	 This is used in the MoveCwR and CmpCwR cases; these are distinguished by a nop following
- 	 the literal load in MoveCwR, and a (self mod: ModReg RM: rX RO: rY) following the CmpCwR."
- 	| base |
- 	base := followingAddress - ((objectMemory byteAt: followingAddress - 1) = 16r90
- 									ifTrue: [9]
- 									ifFalse: [11]).
  	^self cCode: [objectMemory unalignedLongAt: base]
  		inSmalltalk:
  			[   (objectMemory byteAt: base)
  			+ ((objectMemory byteAt: base + 1) << 8)
  			+ ((objectMemory byteAt: base + 2) << 16)
  			+ ((objectMemory byteAt: base + 3) << 24)
  			+ ((objectMemory byteAt: base + 4) << 32)
  			+ ((objectMemory byteAt: base + 5) << 40)
  			+ ((objectMemory byteAt: base + 6) << 48)
  			+ ((objectMemory byteAt: base + 7) << 52)]!

Item was changed:
  ----- Method: CogInLineLiteralsX64Compiler>>pushCwByteSize (in category 'accessing') -----
  pushCwByteSize
+ 	"With in-line literals we use a 12 byte sequence for loading a 64-bit immediate, which
+ 	 is one more than strictly necessary.  The sequence ends with a 16r50 + reg opcode
+ 	 (PushR) to allow us to distinguish between this and the (self mod: ModReg RM: rX RO: rY)
+ 	 at the end of an ArithCwR sequence."
- 	"With in-line literals we use an 9 byte sequence for loading a 64-bit immediate,
- 	 which is one more than strictly necessary.  We plant a nop at the end of the
- 	 sequence to allow us to distinguish between this and the
- 	 (self mod: ModReg RM: rX RO: rY) at the end of an ArithCwR sequence."
  	<inline: true>
+ 	^12!
- 	^9!

Item was added:
+ ----- Method: CogInLineLiteralsX64Compiler>>storeLiteral:beforeFollowingAddress: (in category 'inline cacheing') -----
+ storeLiteral: literal beforeFollowingAddress: followingAddress
+ 	"Rewrite the literal in the instruction immediately preceding followingAddress.
+ 	 This is used in the MoveCwR, PushCwR and CmpCwR cases; these are distinguished by a
+ 	 nop following the literal load in MoveCwR, a 16r50 + reg ending the PushCwR sequence, and
+ 	 a (self mod: ModReg RM: rX RO: rY) ending the CmpCwR sequence, which is at least 16rC0."
+ 	| lastByte base |
+ 	lastByte := objectMemory byteAt: followingAddress - 1.
+ 	base := followingAddress - (lastByte <= 16r90
+ 									ifTrue:
+ 										[lastByte = 16r90
+ 											ifTrue: [9]		"MoveCwR"
+ 											ifFalse: [10]]	"PushCwR"
+ 									ifFalse: [11]).			"ArithCwR"
+ 	self cCode: [objectMemory unalignedLongAt: base put: literal]
+ 		inSmalltalk:
+ 			[objectMemory
+ 				byteAt: base put: (literal bitAnd: 16rFF);
+ 				byteAt: base + 1 put: ((literal >> 8) bitAnd: 16rFF);
+ 				byteAt: base + 2 put: ((literal >> 16) bitAnd: 16rFF);
+ 				byteAt: base + 3 put: ((literal >> 24) bitAnd: 16rFF);
+ 				byteAt: base + 4 put: ((literal >> 32) bitAnd: 16rFF);
+ 				byteAt: base + 5 put: ((literal >> 40) bitAnd: 16rFF);
+ 				byteAt: base + 6 put: ((literal >> 48) bitAnd: 16rFF);
+ 				byteAt: base + 7 put: ((literal >> 52) bitAnd: 16rFF)]!

Item was added:
+ ----- Method: CogOutOfLineLiteralsX64Compiler class>>isConcreteRISCTempRegister: (in category 'testing') -----
+ isConcreteRISCTempRegister: concreteRegister
+ 	"For tests to filter-out bogus values left in the ConcreteRISCTempRegister, if any."
+ 	^false!

Item was changed:
  ----- Method: CogX64Compiler>>concretizeMoveCqR (in category 'generate machine code') -----
  concretizeMoveCqR
  	"Will get inlined into concretizeAt: switch.
  	 On x64 we can short-cut mov 0, reg using xor, and use 32-bit displacement, signed or unsigned, if possible."
  	<inline: true>
  	| value reg |
  	value := operands at: 0.
  	(self is32BitSignedImmediate: value) ifFalse:
  		[^self concretizeMoveCwR].
  	reg := self concreteRegister: (operands at: 1).
- 	machineCode at: 0 put: (self rexR: reg x: 0 b: reg).
  	value = 0 ifTrue:
  		[machineCode
+ 			at: 0 put: (self rexR: reg x: 0 b: reg);
  			at: 1 put: 16r31;
  			at: 2 put: (self mod: ModReg RM: reg RO: reg).
  		^machineCodeSize := 3].
  	machineCode
+ 		at: 0 put: (self rexR: reg x: 0 b: 0);
  		at: 1 put: 16rC7;
  		at: 2 put: (self mod: ModReg RM: reg RO: 0);
  		at: 3 put: (value bitAnd: 16rFF);
  		at: 4 put: (value >> 8 bitAnd: 16rFF);
  		at: 5 put: (value >> 16 bitAnd: 16rFF);
  		at: 6 put: (value >> 24 bitAnd: 16rFF).
  	^machineCodeSize := 7!



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