[Vm-dev] VM Maker: VMMaker.oscog-eem.1831.mcz

commits at source.squeak.org commits at source.squeak.org
Thu Apr 21 23:27:31 UTC 2016


Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1831.mcz

==================== Summary ====================

Name: VMMaker.oscog-eem.1831
Author: eem
Time: 21 April 2016, 4:25:31.011425 pm
UUID: beed3fdd-2d6b-44ae-a973-f30b4dfa61e5
Ancestors: VMMaker.oscog-nice.1830

64-bit Cogit: is32BitSignedImmediate:
 & isSignExtendedFourByteValue: are the same; we only need one.

=============== Diff against VMMaker.oscog-nice.1830 ===============

Item was changed:
  ----- Method: CogInLineLiteralsX64Compiler>>computeSizeOfArithCqR (in category 'generate machine code') -----
  computeSizeOfArithCqR
  	"With CqR we assume constants are 32-bits or less."
  	<inline: true>
  	(self isQuick: (operands at: 0)) ifTrue:
  		[^4].
+ 	(self is32BitSignedImmediate: (operands at: 0)) ifTrue:
- 	(self isSignExtendedFourByteValue: (operands at: 0)) ifTrue:
  		[^(operands at: 1) = RAX ifTrue: [6] ifFalse: [7]].
  	^10 "movabsq" + 3 "r op r"!

Item was changed:
  ----- Method: CogX64Compiler>>computeMaximumSize (in category 'generate machine code') -----
(excessive size, no diff calculated)

Item was changed:
  ----- Method: CogX64Compiler>>concretizeArithCqRWithRO:raxOpcode: (in category 'generate machine code') -----
  concretizeArithCqRWithRO: regOpcode raxOpcode: raxOpcode
  	"Will get inlined into concretizeAt: switch."
  	<inline: false>
  	| value reg |
  	value := operands at: 0.
  	reg := operands at: 1.
  	machineCode
  		at: 0 put: (self rexR: 0 x: 0 b: reg).
  	(self isQuick: value) ifTrue:
  		[machineCode
  			at: 1 put: 16r83;
  			at: 2 put: (self mod: ModReg RM: reg RO: regOpcode);
  			at: 3 put: (value bitAnd: 16rFF).
  		 ^machineCodeSize := 4].
+ 	(self is32BitSignedImmediate: value) ifTrue:
- 	(self isSignExtendedFourByteValue: value) ifTrue:
  		[reg = RAX ifTrue:
  			[machineCode
  				at: 1 put: raxOpcode;
  				at: 2 put: (value bitAnd: 16rFF);
  				at: 3 put: (value >> 8 bitAnd: 16rFF);
  				at: 4 put: (value >> 16 bitAnd: 16rFF);
  				at: 5 put: (value >> 24 bitAnd: 16rFF).
  			 ^machineCodeSize := 6].
  		machineCode
  			at: 1 put: 16r81;
  			at: 2 put: (self mod: ModReg RM: reg RO: regOpcode);
  			at: 3 put: (value bitAnd: 16rFF);
  			at: 4 put: (value >> 8 bitAnd: 16rFF);
  			at: 5 put: (value >> 16 bitAnd: 16rFF);
  			at: 6 put: (value >> 24 bitAnd: 16rFF).
  		 ^machineCodeSize := 7].
  	^self concretizeArithCwR: (raxOpcode = 16r3D "Cmp" ifTrue: [16r39] ifFalse: [raxOpcode - 2])!

Item was changed:
  ----- Method: CogX64Compiler>>concretizePushCq (in category 'generate machine code') -----
  concretizePushCq
  	<inline: true>
  	| value |
  	value := operands at: 0.
  	(self isQuick: value) ifTrue:
  		[machineCode
  			at: 0 put: 16r6A;
  			at: 1 put: (value bitAnd: 16rFF).
  		^machineCodeSize := 2].
+ 	(self is32BitSignedImmediate: value) ifTrue:
- 	(self isSignExtendedFourByteValue: value) ifTrue:
  		[machineCode
  			at: 0 put: 16r68;
  			at: 1 put: (value bitAnd: 16rFF);
  			at: 2 put: (value >> 8 bitAnd: 16rFF);
  			at: 3 put: (value >> 16 bitAnd: 16rFF);
  			at: 4 put: (value >> 24 bitAnd: 16rFF).
  		^machineCodeSize := 5].
  	^self concretizePushCw!

Item was changed:
  ----- Method: CogX64Compiler>>concretizeTstCqR (in category 'generate machine code') -----
  concretizeTstCqR
  	"Will get inlined into concretizeAt: switch."
  	<inline: true>
  	| value reg |
  	value := operands at: 0.
  	reg := operands at: 1.
  	machineCode
  		at: 0 put: (self rexR: 0 x: 0 b: reg).
  	(self isQuick: value) ifTrue:
  		[machineCode
  			at: 1 put: 16rF6;
  			at: 2 put: (self mod: ModReg RM: reg RO: 0);
  			at: 3 put: (value bitAnd: 16rFF).
  		 ^machineCodeSize := 4].
  	
+ 	(self is32BitSignedImmediate: value) ifTrue:
- 	(self isSignExtendedFourByteValue: value) ifTrue:
  		[reg = RAX ifTrue:
  			[machineCode
  				at: 1 put: 16rA9;
  				at: 2 put: (value bitAnd: 16rFF);
  				at: 3 put: (value >> 8 bitAnd: 16rFF);
  				at: 4 put: (value >> 16 bitAnd: 16rFF);
  				at: 5 put: (value >> 24 bitAnd: 16rFF).
  			 ^machineCodeSize := 6].
  		machineCode
  			at: 1 put: 16rF7;
  			at: 2 put: (self mod: ModReg RM: reg RO: 0);
  			at: 3 put: (value bitAnd: 16rFF);
  			at: 4 put: (value >> 8 bitAnd: 16rFF);
  			at: 5 put: (value >> 16 bitAnd: 16rFF);
  			at: 6 put: (value >> 24 bitAnd: 16rFF).
  		 ^machineCodeSize := 7].
  	^self concretizeArithCwR: 16r85!

Item was changed:
  ----- Method: CogX64Compiler>>is32BitSignedImmediate: (in category 'testing') -----
  is32BitSignedImmediate: a64BitUnsignedOperand
+ 	"Top 32 bits all the same as the bottom 32 bits' sign bit implies we can use a sign-extended 4 byte offset."
  	^self cCode: [(self cCoerceSimple: a64BitUnsignedOperand to: #int) = (self cCoerceSimple: a64BitUnsignedOperand to: #long)]
+ 		inSmalltalk: [((a64BitUnsignedOperand >> 32) signedIntFromLong + 1 bitXor: 1) = (a64BitUnsignedOperand >> 31 bitAnd: 1)]!
- 		inSmalltalk: [((a64BitUnsignedOperand >> 32) signedIntFromLong between: -1 and: 0)
- 					and: [(a64BitUnsignedOperand >> 31) signedIntFromLong between: -1 and: 0]]!

Item was removed:
- ----- Method: CogX64Compiler>>isSignExtendedFourByteValue: (in category 'testing') -----
- isSignExtendedFourByteValue: unsigned64BitValue
- 	"Top 32 bits all the same as the bottom 32 bits' sign bit  implies we can use a sign-extended 4 byte offset."
- 	^((self cCode: [unsigned64BitValue >>> 32]
- 			inSmalltalk: [(unsigned64BitValue >> 32) signedIntFromLong]) + 1 bitXor: 1) = (unsigned64BitValue >> 31 bitAnd: 1)!



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