[Vm-dev] Exploring the simulator (was Re: REPL image for simulation)

tim Rowledge tim at rowledge.org
Mon May 30 17:27:47 UTC 2016


> On 30-05-2016, at 10:09 AM, Ben Coman <btc at openinworld.com> wrote:
> 
> 
> On Mon, May 30, 2016 at 11:35 PM, Clément Bera <bera.clement at gmail.com> wrote:
>> 
>> I did a post out of this thread:
>> 
>> https://clementbera.wordpress.com/2016/05/30/simulating-the-cog-vm/
> 
> Nice article Clement, thanks.
> One thing though, I can't think what the "dis" means in genAndDis: ?

Ooh, ooh - I can answer that one! "generate and disassemble” as in generate the code and then disassemble it and display the nicely formatted string result so you can see where it all went horribly wrong.


tim
--
tim Rowledge; tim at rowledge.org; http://www.rowledge.org/tim
The less time planning, the more time programming.




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