[Vm-dev] VM Maker: VMMaker.oscog-cb.1940.mcz

[commits at source.squeak.org]

ClementBera uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-cb.1940.mcz

==================== Summary ====================

Name: VMMaker.oscog-cb.1940
Author: cb
Time: 5 September 2016, 4:30:12.516872 pm
UUID: 2c5c4513-a2d7-4f93-ab3a-168bb35b52c9
Ancestors: VMMaker.oscog-cb.1939

disabled 2 paths compiltion on full blocks.
Improved an assertion.

=============== Diff against VMMaker.oscog-cb.1939 ===============

Item was changed:
  ----- Method: StackToRegisterMappingCogit>>compileFullBlockMethodFrameBuild: (in category 'compile abstract instructions') -----
  compileFullBlockMethodFrameBuild: numCopied
  	<option: #SistaV1BytecodeSet>
+ 	useTwoPaths ifTrue: 
+ 		[ "method with only inst var store, we compile only slow path for now" 
+ 		 useTwoPaths := false.
+ 		 self cppIf: IMMUTABILITY ifTrue: [ needsFrame := true ] ].
  	needsFrame ifFalse:
  		[self assert: numCopied = 0.
  		 self compileFullBlockFramelessEntry: numCopied.
  		 self initSimStackForFramelessBlock: initialPC.
  		 ^self].
  	super compileFullBlockMethodFrameBuild: numCopied.
  	self initSimStackForFramefulMethod: initialPC!

Item was changed:
  ----- Method: StackToRegisterMappingCogit>>initSimStackForFramelessMethod: (in category 'simulation stack') -----
  initSimStackForFramelessMethod: startpc
  	| desc |
  	<var: #desc type: #'CogSimStackEntry *'>
  	simSelf
  		type: SSRegister;
  		spilled: false;
  		register: ReceiverResultReg.
  	optStatus
  		isReceiverResultRegLive: true;
  		ssEntry: (self addressOf: simSelf).
+ 	self assert: methodOrBlockNumTemps = methodOrBlockNumArgs.
- 	self assert: methodOrBlockNumTemps >= methodOrBlockNumArgs.
  	self assert: self numRegArgs <= 2.
  	(methodOrBlockNumArgs between: 1 and: self numRegArgs)
  		ifTrue:
  			[desc := self simStackAt: 0.
  			 desc
  				type: SSRegister;
  				spilled: false;
  				register: Arg0Reg;
  				bcptr: startpc.
  			 methodOrBlockNumArgs > 1 ifTrue:
  				[desc := self simStackAt: 1.
  				 desc
  					type: SSRegister;
  					spilled: false;
  					register: Arg1Reg;
  					bcptr: startpc]]
  		ifFalse:
  			[0 to: methodOrBlockNumArgs - 1 do:
  				[:i|
  				desc := self simStackAt: i.
  				desc
  					type: SSBaseOffset;
  					register: SPReg;
  					spilled: true;
  					offset: ((backEnd hasLinkRegister
  								ifTrue: [methodOrBlockNumArgs - 1- i]
  								ifFalse: [methodOrBlockNumArgs - i]) * objectMemory wordSize);
  					bcptr: startpc]].
  	simSpillBase := simStackPtr := methodOrBlockNumArgs - 1!