[Vm-dev] Time primHighResClock truncated to 32 bits in 64 bits VMs.

tim Rowledge tim at rowledge.org
Sun Dec 31 19:06:28 UTC 2017

> On 31-12-2017, at 4:37 AM, Tobias Pape <Das.Linux at gmx.de> wrote:
>> [snip]
>> As a reminder to fix the ARM part someday, and because I am *so* not going to mess with git right now, here is an extract from 
>> https://www.raspberrypi.org/forums/viewtopic.php?t=30821 "RDTSC on ARM”
> Looks interesting, but since when is this supported?
> When I look for the ARM1176JZF-S Docu (aka Raspberry Pi 1), http://infocenter.arm.com/help/topic/com.arm.doc.ddi0290g/Bihbeabc.html
> the CP15 info (see p15 above) has info on the c9 register, but not with c12 and c13 as second register.
> OTOH, from the ARM Cortex-A7 (aka Raspberry Pi 2), the registers _are_ documented as "Performance monitor Control": http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/BABFIBHD.html
> Do we want to be pi2-above compatible or also below?

Well the older v6 cores are less interesting, at least in Pi-land, because rarer; about 65% of those sold are v7 and over  30% are v7/8. However, it would be lovely to give those older Pi 1’s and the newer Pi 0’s a hires clock and I suspect that we’d use the c15/c12 cycle count register.

The problem is that there is only a 32bit value (in either case) and so we’d have to set up an interrupt to call on overflow and blah-blah-blah. So much more fun to get the v8 Cog done and use the PMU PMCCNTR_EL0 register, which is a proper 64bit reg. Ooh, and it can be set to tick every 64 cycles too, giving a larger range, and even do not tick if  various filters set. I think that’s supposed to allow not-counting of time to do a cache fiddle or whatever. Time for some smart person to pay me to get to work on the v8….

tim Rowledge; tim at rowledge.org; http://www.rowledge.org/tim
Useful random insult:- Life by Norman Rockwell, but screenplay by Stephen King.

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