[Vm-dev] VM Maker: VMMaker.oscog-rsf.2145.mcz
commits at source.squeak.org
commits at source.squeak.org
Mon Mar 6 08:36:27 UTC 2017
Ronie Salgado Faila uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-rsf.2145.mcz
==================== Summary ====================
Name: VMMaker.oscog-rsf.2145
Author: rsf
Time: 6 March 2017, 5:35:20.115331 am
UUID: 65262519-75c7-4e77-b531-4c7c5838a206
Ancestors: VMMaker.oscog-eem.2144
Refactoring the register allocation for the Lowcode instructions. The new register allocators are not yet tested because an error on the previous does not allow me to generate the sources for testing the refactoring.
=============== Diff against VMMaker.oscog-eem.2144 ===============
Item was changed:
----- Method: CCodeGenerator>>initializeCTranslationDictionary (in category 'C translation support') -----
initializeCTranslationDictionary
"Initialize the dictionary mapping message names to actions for C code generation."
| pairs |
translationDict := Dictionary new: 200.
pairs := #(
#& #generateAnd:on:indent:
#| #generateOr:on:indent:
#abs #generateAbs:on:indent:
#and: #generateSequentialAnd:on:indent:
#or: #generateSequentialOr:on:indent:
#not #generateNot:on:indent:
#+ #generatePlus:on:indent:
#- #generateMinus:on:indent:
#negated #generateNegated:on:indent:
#* #generateTimes:on:indent:
#/ #generateDivide:on:indent:
#// #generateDivide:on:indent:
#\\ #generateModulo:on:indent:
#<< #generateShiftLeft:on:indent:
#>> #generateShiftRight:on:indent:
#>>> #generateSignedShiftRight:on:indent:
#min: #generateMin:on:indent:
#max: #generateMax:on:indent:
#between:and: #generateBetweenAnd:on:indent:
#bitAnd: #generateBitAnd:on:indent:
#bitOr: #generateBitOr:on:indent:
#bitXor: #generateBitXor:on:indent:
#bitShift: #generateBitShift:on:indent:
#signedBitShift: #generateSignedBitShift:on:indent:
#bitInvert32 #generateBitInvert:on:indent:
#bitInvert64 #generateBitInvert:on:indent:
#bitClear: #generateBitClear:on:indent:
#truncateTo: #generateTruncateTo:on:indent:
#rounded #generateRounded:on:indent:
#byteSwap32 #generateByteSwap32:on:indent:
#byteSwap64 #generateByteSwap64:on:indent:
#byteSwapped32IfBigEndian: generateByteSwap32IfBigEndian:on:indent:
#byteSwapped64IfBigEndian: generateByteSwap64IfBigEndian:on:indent:
#< #generateLessThan:on:indent:
#<= #generateLessThanOrEqual:on:indent:
#= #generateEqual:on:indent:
#> #generateGreaterThan:on:indent:
#>= #generateGreaterThanOrEqual:on:indent:
#~= #generateNotEqual:on:indent:
#== #generateEqual:on:indent:
#~~ #generateNotEqual:on:indent:
#isNil #generateIsNil:on:indent:
#notNil #generateNotNil:on:indent:
#whileTrue: #generateWhileTrue:on:indent:
#whileFalse: #generateWhileFalse:on:indent:
#whileTrue #generateDoWhileTrue:on:indent:
#whileFalse #generateDoWhileFalse:on:indent:
#to:do: #generateToDo:on:indent:
#to:by:do: #generateToByDo:on:indent:
#repeat #generateRepeat:on:indent:
#timesRepeat: #generateTimesRepeat:on:indent:
#ifTrue: #generateIfTrue:on:indent:
#ifFalse: #generateIfFalse:on:indent:
#ifTrue:ifFalse: #generateIfTrueIfFalse:on:indent:
#ifFalse:ifTrue: #generateIfFalseIfTrue:on:indent:
#ifNotNil: #generateIfNotNil:on:indent:
#ifNil: #generateIfNil:on:indent:
#ifNotNil:ifNil: #generateIfNotNilIfNil:on:indent:
#ifNil:ifNotNil: #generateIfNilIfNotNil:on:indent:
#at: #generateAt:on:indent:
#at:put: #generateAtPut:on:indent:
#basicAt: #generateAt:on:indent:
#basicAt:put: #generateAtPut:on:indent:
#integerValueOf: #generateIntegerValueOf:on:indent:
#integerObjectOf: #generateIntegerObjectOf:on:indent:
#isIntegerObject: #generateIsIntegerObject:on:indent:
#cCode: #generateInlineCCode:on:indent:
#cCode:inSmalltalk: #generateInlineCCode:on:indent:
#cPreprocessorDirective: #generateInlineCPreprocessorDirective:on:indent:
#cppIf:ifTrue:ifFalse: #generateInlineCppIfElse:on:indent:
#cppIf:ifTrue: #generateInlineCppIfElse:on:indent:
#cCoerce:to: #generateCCoercion:on:indent:
#cCoerceSimple:to: #generateCCoercion:on:indent:
#addressOf: #generateAddressOf:on:indent:
#addressOf:put: #generateAddressOf:on:indent:
#asAddress:put: #generateAsAddress:on:indent:
#signedIntFromLong64 #generateSignedIntFromLong64:on:indent:
#signedIntFromLong #generateSignedIntFromLong:on:indent:
#signedIntFromShort #generateSignedIntFromShort:on:indent:
#signedIntToLong64 #generateSignedIntToLong64:on:indent:
#signedIntToLong #generateSignedIntToLong:on:indent:
#signedIntToShort #generateSignedIntToShort:on:indent:
#preIncrement #generatePreIncrement:on:indent:
#preDecrement #generatePreDecrement:on:indent:
#inline: #generateInlineDirective:on:indent:
#asFloat #generateAsFloat:on:indent:
#asInteger #generateAsInteger:on:indent:
#asIntegerPtr #generateAsIntegerPtr:on:indent:
#asUnsignedInteger #generateAsUnsignedInteger:on:indent:
#asUnsignedIntegerPtr #generateAsUnsignedIntegerPtr:on:indent:
#asLong #generateAsLong:on:indent:
#asUnsignedLong #generateAsUnsignedLong:on:indent:
#asUnsignedLongLong #generateAsUnsignedLongLong:on:indent:
#asVoidPointer #generateAsVoidPointer:on:indent:
#asSymbol #generateAsSymbol:on:indent:
#flag: #generateFlag:on:indent:
#anyMask: #generateBitAnd:on:indent:
#allMask: #generateAllMask:on:indent:
#noMask: #generateNoMask:on:indent:
#raisedTo: #generateRaisedTo:on:indent:
#touch: #generateTouch:on:indent:
#bytesPerOop #generateBytesPerOop:on:indent:
#bytesPerWord #generateBytesPerWord:on:indent:
#wordSize #generateBytesPerWord:on:indent:
#baseHeaderSize #generateBaseHeaderSize:on:indent:
#minSmallInteger #generateSmallIntegerConstant:on:indent:
#maxSmallInteger #generateSmallIntegerConstant:on:indent:
#sharedCodeNamed:inCase: #generateSharedCodeDirective:on:indent:
#perform: #generatePerform:on:indent:
#perform:with: #generatePerform:on:indent:
#perform:with:with: #generatePerform:on:indent:
#perform:with:with:with: #generatePerform:on:indent:
#perform:with:with:with:with: #generatePerform:on:indent:
#perform:with:with:with:with:with: #generatePerform:on:indent:
#value #generateValue:on:indent:
#value: #generateValue:on:indent:
#value:value: #generateValue:on:indent:
#value:value:value: #generateValue:on:indent:
#value:value:value:value: #generateValue:on:indent:
+ #value:value:value:value:value: #generateValue:on:indent:
+ #value:value:value:value:value:value: #generateValue:on:indent:
#deny: #generateDeny:on:indent:
#shouldNotImplement #generateSmalltalkMetaError:on:indent:
#shouldBeImplemented #generateSmalltalkMetaError:on:indent:
#subclassResponsibility #generateSmalltalkMetaError:on:indent:
).
1 to: pairs size by: 2 do: [:i |
translationDict at: (pairs at: i) put: (pairs at: i + 1)].
pairs := #(
#ifTrue: #generateIfTrueAsArgument:on:indent:
#ifFalse: #generateIfFalseAsArgument:on:indent:
#ifTrue:ifFalse: #generateIfTrueIfFalseAsArgument:on:indent:
#ifFalse:ifTrue: #generateIfFalseIfTrueAsArgument:on:indent:
#ifNotNil: #generateIfNotNilAsArgument:on:indent:
#ifNil: #generateIfNilAsArgument:on:indent:
#ifNotNil:ifNil: #generateIfNotNilIfNilAsArgument:on:indent:
#ifNil:ifNotNil: #generateIfNilIfNotNilAsArgument:on:indent:
#cCode: #generateInlineCCodeAsArgument:on:indent:
#cCode:inSmalltalk: #generateInlineCCodeAsArgument:on:indent:
#cppIf:ifTrue:ifFalse: #generateInlineCppIfElseAsArgument:on:indent:
#cppIf:ifTrue: #generateInlineCppIfElseAsArgument:on:indent:
#value #generateValueAsArgument:on:indent:
#value: #generateValueAsArgument:on:indent:
#value:value: #generateValueAsArgument:on:indent:
).
asArgumentTranslationDict := Dictionary new: 8.
1 to: pairs size by: 2 do: [:i |
asArgumentTranslationDict at: (pairs at: i) put: (pairs at: i + 1)].
!
Item was added:
+ ----- Method: CogSimStackNativeEntry>>nativeRegisterSecondOrNone (in category 'accessing') -----
+ nativeRegisterSecondOrNone
+ ^type = SSRegisterPair
+ ifTrue: [registerSecond]
+ ifFalse: [NoReg]!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateFloatRegNotConflictingWith: (in category 'simulation stack') -----
+ allocateFloatRegNotConflictingWith: regMask
+ | reg |
+ "if there's a free register, use it"
+ reg := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: regMask).
+ reg = NoReg ifTrue: "No free register, choose one that does not conflict with regMask"
+ [reg := self freeAnyFloatRegNotConflictingWith: regMask].
+ ^ reg!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeFloat2: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeFloat2: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rNext rTop topRegistersMask |
+ topRegistersMask := 0.
+ rTop := rNext := NoReg.
+
+ self ssNativeTop nativeFloatRegisterOrNone ~= NoReg ifTrue:
+ [ rTop := self ssNativeTop nativeFloatRegisterOrNone].
+ (self ssNativeValue: 1) nativeFloatRegisterOrNone ~= NoReg ifTrue:
+ [ topRegistersMask := self registerMaskFor: (rNext := (self ssNativeValue: 1) nativeFloatRegisterOrNone)].
+
+ rTop = NoReg ifTrue:
+ [ rTop := self allocateFloatRegNotConflictingWith: topRegistersMask ].
+
+ rNext = NoReg ifTrue:
+ [ rNext := self allocateFloatRegNotConflictingWith: (self registerMaskFor: rTop) ].
+ self deny: (rTop = NoReg or: [rNext = NoReg]).
+
+ ^ aBlock value: rTop value: rNext
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeFloat2ResultInteger: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeFloat2ResultInteger: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | frNext frTop topRegistersMask rResult |
+ topRegistersMask := 0.
+ frTop := frNext := NoReg.
+ rResult := NoReg.
+
+ self ssNativeTop nativeFloatRegisterOrNone ~= NoReg ifTrue:
+ [ frTop := self ssNativeTop nativeFloatRegisterOrNone].
+ (self ssNativeValue: 1) nativeFloatRegisterOrNone ~= NoReg ifTrue:
+ [ topRegistersMask := self registerMaskFor: (frNext := (self ssNativeValue: 1) nativeFloatRegisterOrNone)].
+
+ frTop = NoReg ifTrue:
+ [ frTop := self allocateFloatRegNotConflictingWith: topRegistersMask ].
+
+ frNext = NoReg ifTrue:
+ [ frNext := self allocateFloatRegNotConflictingWith: (self registerMaskFor: frTop) ].
+
+ "Result"
+ rResult := self allocateRegNotConflictingWith: 0.
+
+ self deny: (frTop = NoReg or: [frNext = NoReg or: [rResult]]).
+
+ ^ aBlock value: frTop value: frNext value: rResult
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeFloat: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeFloat: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | frTop topRegistersMask |
+ topRegistersMask := 0.
+ frTop := NoReg.
+
+ self ssNativeTop nativeFloatRegisterOrNone ~= NoReg ifTrue:
+ [ frTop := self ssNativeTop nativeFloatRegisterOrNone].
+
+ frTop = NoReg ifTrue:
+ [ frTop := self allocateFloatRegNotConflictingWith: topRegistersMask ].
+ self deny: (frTop = NoReg).
+
+ ^ aBlock value: frTop
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeFloatInteger: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeFloatInteger: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ "Used by storeFloat32ToMemory and storeFloat64ToMemory"
+ | frTop rTop |
+ frTop := rTop := NoReg.
+
+ "Integer registers"
+ self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue:
+ [ rTop := self ssNativeTop nativeRegisterOrNone].
+
+ rTop = NoReg ifTrue:
+ [ rTop := self allocateRegNotConflictingWith: 0 ].
+
+ "Float registers"
+ (self ssNativeValue: 1) nativeFloatRegisterOrNone ~= NoReg ifTrue:
+ [ frTop := (self ssNativeValue: 1) nativeFloatRegisterOrNone].
+
+ frTop = NoReg ifTrue:
+ [ frTop := self allocateFloatRegNotConflictingWith: 0 ].
+
+ self deny: (frTop = NoReg or: [rTop = NoReg]).
+
+ ^ aBlock value: frTop value: rTop!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeFloatResultFloat: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeFloatResultFloat: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | frTop frResult |
+ frTop := NoReg.
+ frResult := NoReg.
+
+ "Float argument"
+ self ssNativeTop nativeFloatRegisterOrNone ~= NoReg ifTrue:
+ [ frTop := self ssNativeTop nativeFloatRegisterOrNone].
+
+ frTop = NoReg ifTrue:
+ [ frTop := self allocateFloatRegNotConflictingWith: self emptyRegisterMask ].
+
+ "Float result".
+ frResult := self allocateFloatRegNotConflictingWith: (self registerMaskFor: frTop).
+ self deny: (frTop = NoReg or: [frResult = NoReg]).
+
+ ^ aBlock value: frTop value: frResult
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeFloatResultInteger2: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeFloatResultInteger2: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | frTop rResult rResult2 |
+ frTop := NoReg.
+ rResult2 := rResult := NoReg.
+
+ "Float argument"
+ self ssNativeTop nativeFloatRegisterOrNone ~= NoReg ifTrue:
+ [ frTop := self ssNativeTop nativeFloatRegisterOrNone].
+
+ frTop = NoReg ifTrue:
+ [ frTop := self allocateFloatRegNotConflictingWith: self emptyRegisterMask ].
+
+ "Integer result".
+ rResult := self allocateRegNotConflictingWith: (self emptyRegisterMask).
+ rResult2 := self allocateRegNotConflictingWith: (self registerMaskFor: rResult).
+
+ self deny: (frTop = NoReg or: [rResult = NoReg or: [rResult2 = NoReg]]).
+
+ ^ aBlock value: frTop value: rResult value: rResult2
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeFloatResultInteger: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeFloatResultInteger: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | frTop rResult |
+ frTop := NoReg.
+ rResult := NoReg.
+
+ "Float argument"
+ self ssNativeTop nativeFloatRegisterOrNone ~= NoReg ifTrue:
+ [ frTop := self ssNativeTop nativeFloatRegisterOrNone].
+
+ frTop = NoReg ifTrue:
+ [ frTop := self allocateFloatRegNotConflictingWith: self emptyRegisterMask ].
+
+ "Integer result".
+ rResult := self allocateRegNotConflictingWith: (self emptyRegisterMask).
+
+ self deny: (frTop = NoReg or: [rResult = NoReg]).
+
+ ^ aBlock value: frTop value: rResult
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeFloatResultOop: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeFloatResultOop: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | frTop rResult |
+ frTop := NoReg.
+ rResult := NoReg.
+
+ "Float argument"
+ self ssNativeTop nativeFloatRegisterOrNone ~= NoReg ifTrue:
+ [ frTop := self ssNativeTop nativeFloatRegisterOrNone].
+
+ frTop = NoReg ifTrue:
+ [ frTop := self allocateFloatRegNotConflictingWith: self emptyRegisterMask ].
+
+ "Integer result".
+ rResult := self allocateRegNotConflictingWith: (self emptyRegisterMask).
+
+ self deny: (frTop = NoReg or: [rResult = NoReg]).
+
+ ^ aBlock value: frTop value: rResult
+
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger2: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeInteger2: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rNext rTop topRegistersMask |
+ topRegistersMask := 0.
+ rTop := rNext := NoReg.
+
+ self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [
+ rTop := self ssNativeTop nativeRegisterOrNone.
+ self ssNativeTop nativeRegisterSecondOrNone ~= NoReg ifTrue:
+ [ rNext := self ssNativeTop nativeRegisterSecondOrNone]
+ ].
+
+ rNext = NoReg ifTrue: [
+ (self ssNativeValue: 1) nativeRegisterOrNone ~= NoReg ifTrue:
+ [ topRegistersMask := self registerMaskFor: (rNext := (self ssNativeValue: 1) nativeRegisterOrNone)].
+ ].
+
+ rTop = NoReg ifTrue:
+ [ rTop := self allocateRegNotConflictingWith: topRegistersMask ].
+
+ rNext = NoReg ifTrue:
+ [ rNext := self allocateRegNotConflictingWith: (self registerMaskFor: rTop) ].
+
+ self deny: (rTop = NoReg or: [rNext = NoReg]).
+ ^ aBlock value: rTop value: rNext
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger2ResultFloat: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeInteger2ResultFloat: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rNext rTop topRegistersMask frResult |
+ topRegistersMask := 0.
+ rTop := rNext := NoReg.
+ frResult := NoReg
+
+ self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [
+ rTop := self ssNativeTop nativeRegisterOrNone.
+ self ssNativeTop nativeRegisterSecondOrNone ~= NoReg ifTrue:
+ [ rNext := self ssNativeTop nativeRegisterSecondOrNone]
+ ].
+
+ rNext = NoReg ifTrue: [
+ (self ssNativeValue: 1) nativeRegisterOrNone ~= NoReg ifTrue:
+ [ topRegistersMask := self registerMaskFor: (rNext := (self ssNativeValue: 1) nativeRegisterOrNone)].
+ ].
+
+ rTop = NoReg ifTrue:
+ [ rTop := self allocateRegNotConflictingWith: topRegistersMask ].
+
+ rNext = NoReg ifTrue:
+ [ rNext := self allocateRegNotConflictingWith: (self registerMaskFor: rTop) ].
+
+ "Results"
+ frResult := self allocateFloatRegNotConflictingWith: self emptyRegisterMask.
+
+ self deny: (rTop = NoReg or: [rNext = NoReg or: [frResult = NoReg]]).
+
+ ^ aBlock value: rTop value: rNext value: frResult!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger2ResultInteger2: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeInteger2ResultInteger2: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rNext rTop topRegistersMask rResult rResult2 |
+ topRegistersMask := 0.
+ rTop := rNext := NoReg.
+ rResult := rResult2 := NoReg
+
+ self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [
+ rTop := self ssNativeTop nativeRegisterOrNone.
+ self ssNativeTop nativeRegisterSecondOrNone ~= NoReg ifTrue:
+ [ rNext := self ssNativeTop nativeRegisterSecondOrNone]
+ ].
+
+ rNext = NoReg ifTrue: [
+ (self ssNativeValue: 1) nativeRegisterOrNone ~= NoReg ifTrue:
+ [ topRegistersMask := self registerMaskFor: (rNext := (self ssNativeValue: 1) nativeRegisterOrNone)].
+ ].
+
+ rTop = NoReg ifTrue:
+ [ rTop := self allocateRegNotConflictingWith: topRegistersMask ].
+
+ rNext = NoReg ifTrue:
+ [ rNext := self allocateRegNotConflictingWith: (self registerMaskFor: rTop) ].
+
+ self deny: (rTop = NoReg or: [rNext = NoReg]).
+
+ "Results"
+ rResult := self allocateFloatRegNotConflictingWith: (self registerMaskFor: rTop and: rNext).
+ rResult2 := self allocateFloatRegNotConflictingWith: (self registerMaskFor: rTop and: rNext and: rResult).
+ self deny: (rResult = NoReg or: [rResult2 = NoReg]).
+
+ ^ aBlock value: rTop value: rNext value: rResult value: rResult2!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger2ResultInteger: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeInteger2ResultInteger: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rNext rTop topRegistersMask rResult |
+ topRegistersMask := 0.
+ rTop := rNext := NoReg.
+ rResult := NoReg
+
+ self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [
+ rTop := self ssNativeTop nativeRegisterOrNone.
+ self ssNativeTop nativeRegisterSecondOrNone ~= NoReg ifTrue:
+ [ rNext := self ssNativeTop nativeRegisterSecondOrNone]
+ ].
+
+ rNext = NoReg ifTrue: [
+ (self ssNativeValue: 1) nativeRegisterOrNone ~= NoReg ifTrue:
+ [ topRegistersMask := self registerMaskFor: (rNext := (self ssNativeValue: 1) nativeRegisterOrNone)].
+ ].
+
+ rTop = NoReg ifTrue:
+ [ rTop := self allocateRegNotConflictingWith: topRegistersMask ].
+
+ rNext = NoReg ifTrue:
+ [ rNext := self allocateRegNotConflictingWith: (self registerMaskFor: rTop) ].
+
+ self deny: (rTop = NoReg or: [rNext = NoReg]).
+
+ "Results"
+ rResult := self allocateFloatRegNotConflictingWith: (self registerMaskFor: rTop and: rNext).
+ self deny: (rResult = NoReg).
+
+ ^ aBlock value: rTop value: rNext value: rResult!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger2ResultOop: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeInteger2ResultOop: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rNext rTop topRegistersMask rResult |
+ topRegistersMask := 0.
+ rTop := rNext := NoReg.
+ rResult := NoReg
+
+ self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [
+ rTop := self ssNativeTop nativeRegisterOrNone.
+ self ssNativeTop nativeRegisterSecondOrNone ~= NoReg ifTrue:
+ [ rNext := self ssNativeTop nativeRegisterSecondOrNone]
+ ].
+
+ rNext = NoReg ifTrue: [
+ (self ssNativeValue: 1) nativeRegisterOrNone ~= NoReg ifTrue:
+ [ topRegistersMask := self registerMaskFor: (rNext := (self ssNativeValue: 1) nativeRegisterOrNone)].
+ ].
+
+ rTop = NoReg ifTrue:
+ [ rTop := self allocateRegNotConflictingWith: topRegistersMask ].
+
+ rNext = NoReg ifTrue:
+ [ rNext := self allocateRegNotConflictingWith: (self registerMaskFor: rTop) ].
+
+ self deny: (rTop = NoReg or: [rNext = NoReg]).
+
+ "Results"
+ rResult := self allocateFloatRegNotConflictingWith: (self registerMaskFor: rTop and: rNext).
+ self deny: (rResult = NoReg).
+
+ ^ aBlock value: rTop value: rNext value: rResult!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger3: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeInteger3: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rNext rNextNext nativeValueIndex rTop registerMask |
+ rTop := rNext := rNextNext := NoReg.
+ nativeValueIndex := 1.
+
+ self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [
+ rTop := self ssNativeTop nativeRegisterOrNone.
+ self ssNativeTop nativeRegisterSecondOrNone ~= NoReg ifTrue:
+ [ rNext := self ssNativeTop nativeRegisterSecondOrNone]
+ ].
+
+ rNext = NoReg ifTrue: [
+ (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [
+ rNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone.
+ (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone ~= NoReg ifTrue: [
+ rNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone.
+ ].
+ nativeValueIndex := nativeValueIndex + 1
+ ].
+ ].
+
+ rNextNext = NoReg ifTrue: [
+ (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [
+ rNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone.
+ ].
+ ].
+
+ rTop = NoReg ifTrue: [
+ registerMask := 0.
+ rNext ~= NoReg ifTrue: [ registerMask := self registerMaskFor: rNext].
+ rNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNext)].
+ rTop := self allocateRegNotConflictingWith: registerMask
+ ].
+
+ rNext = NoReg ifTrue: [
+ registerMask := self registerMaskFor: rTop.
+ rNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNext)].
+ rNext := self allocateRegNotConflictingWith: registerMask
+ ].
+
+ rNextNext = NoReg ifTrue: [
+ registerMask := self registerMaskFor: rTop and: rNext.
+ rNextNext := self allocateRegNotConflictingWith: registerMask
+ ].
+
+ self deny: (rTop = NoReg or: [rNext = NoReg or: [rNextNext = NoReg]]).
+ ^ aBlock value: rTop value: rNext value: rNextNext
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger3ResultInteger: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeInteger3ResultInteger: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rNext rNextNext rResult nativeValueIndex rTop registerMask |
+ rTop := rNext := rNextNext := NoReg.
+ nativeValueIndex := 1.
+
+ self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [
+ rTop := self ssNativeTop nativeRegisterOrNone.
+ self ssNativeTop nativeRegisterSecondOrNone ~= NoReg ifTrue:
+ [ rNext := self ssNativeTop nativeRegisterSecondOrNone]
+ ].
+
+ rNext = NoReg ifTrue: [
+ (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [
+ rNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone.
+ (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone ~= NoReg ifTrue: [
+ rNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone.
+ ].
+ nativeValueIndex := nativeValueIndex + 1
+ ].
+ ].
+
+ rNextNext = NoReg ifTrue: [
+ (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [
+ rNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone.
+ ].
+ ].
+
+ rTop = NoReg ifTrue: [
+ registerMask := 0.
+ rNext ~= NoReg ifTrue: [ registerMask := self registerMaskFor: rNext].
+ rNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNext)].
+ rTop := self allocateRegNotConflictingWith: registerMask
+ ].
+
+ rNext = NoReg ifTrue: [
+ registerMask := self registerMaskFor: rTop.
+ rNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNext)].
+ rNext := self allocateRegNotConflictingWith: registerMask
+ ].
+
+ rNextNext = NoReg ifTrue: [
+ registerMask := self registerMaskFor: rTop and: rNext.
+ rNextNext := self allocateRegNotConflictingWith: registerMask
+ ].
+
+ self deny: (rTop = NoReg or: [rNext = NoReg or: [rNextNext = NoReg]]).
+
+ "Allocate the result"
+ rResult := self allocateRegNotConflictingWith: (self registerMaskFor: rTop and: rNext and: rNextNext).
+ self deny: (rResult = NoReg).
+
+ ^ aBlock value: rTop value: rNext value: rNextNext value: rResult
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger4: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeInteger4: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rNext rNextNext rNextNextNext nativeValueIndex rTop registerMask |
+ rTop := rNext := rNextNext := rNextNextNext := NoReg.
+ nativeValueIndex := 1.
+
+ self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [
+ rTop := self ssNativeTop nativeRegisterOrNone.
+ self ssNativeTop nativeRegisterSecondOrNone ~= NoReg ifTrue:
+ [ rNext := self ssNativeTop nativeRegisterSecondOrNone]
+ ].
+
+ rNext = NoReg ifTrue: [
+ (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [
+ rNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone.
+ (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone ~= NoReg ifTrue: [
+ rNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone.
+ ].
+ nativeValueIndex := nativeValueIndex + 1
+ ].
+ ].
+
+ rNextNext = NoReg ifTrue: [
+ (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [
+ rNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone.
+ (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone ~= NoReg ifTrue: [
+ rNextNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone.
+ ].
+ nativeValueIndex := nativeValueIndex + 1
+ ].
+ ].
+
+ rNextNextNext = NoReg ifTrue: [
+ (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [
+ rNextNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone.
+ nativeValueIndex := nativeValueIndex + 1
+ ].
+ ].
+
+ rTop = NoReg ifTrue: [
+ registerMask := 0.
+ rNext ~= NoReg ifTrue: [ registerMask := self registerMaskFor: rNext].
+ rNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNext)].
+ rNextNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNextNext)].
+ rTop := self allocateRegNotConflictingWith: registerMask
+ ].
+
+ rNext = NoReg ifTrue: [
+ registerMask := self registerMaskFor: rTop.
+ rNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNext)].
+ rNextNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNextNext)].
+ rNext := self allocateRegNotConflictingWith: registerMask
+ ].
+
+ rNextNext = NoReg ifTrue: [
+ registerMask := self registerMaskFor: rTop and: rNext.
+ rNextNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNextNext)].
+ rNextNext := self allocateRegNotConflictingWith: registerMask
+ ].
+
+ rNextNextNext = NoReg ifTrue: [
+ registerMask := self registerMaskFor: rTop and: rNext and: rNextNext.
+ rNextNextNext := self allocateRegNotConflictingWith: registerMask
+ ].
+
+ self deny: (rTop = NoReg or: [rNext = NoReg or: [rNextNext = NoReg or: [rNextNextNext = NoReg]]]).
+ ^ aBlock value: rTop value: rNext value: rNextNext value: rNextNextNext
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger4ResultInteger2: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeInteger4ResultInteger2: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rNext rNextNext rNextNextNext nativeValueIndex rTop registerMask rResult rResult2 |
+ rTop := rNext := rNextNext := rNextNextNext := NoReg.
+ rResult := rResult2 := NoReg.
+ nativeValueIndex := 1.
+
+ self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [
+ rTop := self ssNativeTop nativeRegisterOrNone.
+ self ssNativeTop nativeRegisterSecondOrNone ~= NoReg ifTrue:
+ [ rNext := self ssNativeTop nativeRegisterSecondOrNone]
+ ].
+
+ rNext = NoReg ifTrue: [
+ (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [
+ rNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone.
+ (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone ~= NoReg ifTrue: [
+ rNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone.
+ ].
+ nativeValueIndex := nativeValueIndex + 1
+ ].
+ ].
+
+ rNextNext = NoReg ifTrue: [
+ (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [
+ rNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone.
+ (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone ~= NoReg ifTrue: [
+ rNextNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone.
+ ].
+ nativeValueIndex := nativeValueIndex + 1
+ ].
+ ].
+
+ rNextNextNext = NoReg ifTrue: [
+ (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [
+ rNextNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone.
+ nativeValueIndex := nativeValueIndex + 1
+ ].
+ ].
+
+ rTop = NoReg ifTrue: [
+ registerMask := 0.
+ rNext ~= NoReg ifTrue: [ registerMask := self registerMaskFor: rNext].
+ rNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNext)].
+ rNextNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNextNext)].
+ rTop := self allocateRegNotConflictingWith: registerMask
+ ].
+
+ rNext = NoReg ifTrue: [
+ registerMask := self registerMaskFor: rTop.
+ rNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNext)].
+ rNextNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNextNext)].
+ rNext := self allocateRegNotConflictingWith: registerMask
+ ].
+
+ rNextNext = NoReg ifTrue: [
+ registerMask := self registerMaskFor: rTop and: rNext.
+ rNextNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNextNext)].
+ rNextNext := self allocateRegNotConflictingWith: registerMask
+ ].
+
+ rNextNextNext = NoReg ifTrue: [
+ registerMask := self registerMaskFor: rTop and: rNext and: rNextNext.
+ rNextNextNext := self allocateRegNotConflictingWith: registerMask
+ ].
+
+ self deny: (rTop = NoReg or: [rNext = NoReg or: [rNextNext = NoReg or: [rNextNextNext = NoReg]]]).
+
+ "Result registers"
+ rResult := self allocateRegNotConflictingWith: (self registerMaskFor: rTop and: rNext and: rNextNext and: rNextNextNext).
+ rResult2 := self allocateRegNotConflictingWith: (self registerMaskFor: rTop and: rNext and: rNextNext and: rNextNextNext and: rResult).
+
+ ^ aBlock value: rTop value: rNext value: rNextNext value: rNextNextNext value: rResult value: rResult2
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger4ResultInteger: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeInteger4ResultInteger: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rNext rNextNext rNextNextNext nativeValueIndex rTop registerMask rResult |
+ rTop := rNext := rNextNext := rNextNextNext := NoReg.
+ rResult := NoReg.
+ nativeValueIndex := 1.
+
+ self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [
+ rTop := self ssNativeTop nativeRegisterOrNone.
+ self ssNativeTop nativeRegisterSecondOrNone ~= NoReg ifTrue:
+ [ rNext := self ssNativeTop nativeRegisterSecondOrNone]
+ ].
+
+ rNext = NoReg ifTrue: [
+ (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [
+ rNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone.
+ (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone ~= NoReg ifTrue: [
+ rNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone.
+ ].
+ nativeValueIndex := nativeValueIndex + 1
+ ].
+ ].
+
+ rNextNext = NoReg ifTrue: [
+ (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [
+ rNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone.
+ (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone ~= NoReg ifTrue: [
+ rNextNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterSecondOrNone.
+ ].
+ nativeValueIndex := nativeValueIndex + 1
+ ].
+ ].
+
+ rNextNextNext = NoReg ifTrue: [
+ (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone ~= NoReg ifTrue: [
+ rNextNextNext := (self ssNativeValue: nativeValueIndex) nativeRegisterOrNone.
+ nativeValueIndex := nativeValueIndex + 1
+ ].
+ ].
+
+ rTop = NoReg ifTrue: [
+ registerMask := 0.
+ rNext ~= NoReg ifTrue: [ registerMask := self registerMaskFor: rNext].
+ rNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNext)].
+ rNextNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNextNext)].
+ rTop := self allocateRegNotConflictingWith: registerMask
+ ].
+
+ rNext = NoReg ifTrue: [
+ registerMask := self registerMaskFor: rTop.
+ rNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNext)].
+ rNextNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNextNext)].
+ rNext := self allocateRegNotConflictingWith: registerMask
+ ].
+
+ rNextNext = NoReg ifTrue: [
+ registerMask := self registerMaskFor: rTop and: rNext.
+ rNextNextNext ~= NoReg ifTrue: [ registerMask := registerMask bitOr: (self registerMaskFor: rNextNextNext)].
+ rNextNext := self allocateRegNotConflictingWith: registerMask
+ ].
+
+ rNextNextNext = NoReg ifTrue: [
+ registerMask := self registerMaskFor: rTop and: rNext and: rNextNext.
+ rNextNextNext := self allocateRegNotConflictingWith: registerMask
+ ].
+
+ self deny: (rTop = NoReg or: [rNext = NoReg or: [rNextNext = NoReg or: [rNextNextNext = NoReg]]]).
+
+ "Result registers"
+ rResult := self allocateRegNotConflictingWith: (self registerMaskFor: rTop and: rNext and: rNextNext and: rNextNextNext).
+
+ ^ aBlock value: rTop value: rNext value: rNextNext value: rNextNextNext value: rResult
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger7ResultInteger: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeInteger7ResultInteger: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+ "Effective address 64. This instruction should not be generated on 32-bits mode"
+ self abort
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeInteger: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeInteger: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rTop |
+ rTop := NoReg.
+
+ self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [
+ rTop := self ssNativeTop nativeRegisterOrNone.
+ ].
+
+ rTop = NoReg ifTrue:
+ [ rTop := self allocateRegNotConflictingWith: self emptyRegisterMask].
+
+ self deny: (rTop = NoReg).
+ ^ aBlock value: rTop
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeIntegerOop2: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeIntegerOop2: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rTop rOopTop rOopNext topRegisterMask oopTopRegisterMask |
+ rTop := rOopTop := rOopNext := NoReg.
+ oopTopRegisterMask := topRegisterMask := 0.
+
+ self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [
+ rTop := self ssNativeTop nativeRegisterOrNone.
+ oopTopRegisterMask := self registerMaskFor: rTop.
+ ].
+
+ self ssTop registerOrNone ~= NoReg ifTrue: [
+ rOopTop := self ssTop registerOrNone.
+ topRegisterMask := self registerMaskFor: rOopTop.
+ ].
+
+ (self ssValue: 1) registerOrNone ~= NoReg ifTrue: [
+ rOopNext := (self ssValue: 1) registerOrNone.
+ topRegisterMask := topRegisterMask bitOr: (self registerMaskFor: rOopNext).
+ oopTopRegisterMask := oopTopRegisterMask bitOr: (self registerMaskFor: rOopNext).
+ ].
+
+ rTop = NoReg ifTrue: [
+ rTop := self allocateRegNotConflictingWith: topRegisterMask
+ ].
+
+ rOopTop = NoReg ifTrue: [
+ rOopTop := self allocateRegNotConflictingWith: oopTopRegisterMask
+ ].
+
+ rOopNext = NoReg ifTrue: [
+ rOopNext := self allocateRegNotConflictingWith: (self registerMaskFor: rTop and: rOopTop)
+ ].
+
+ self deny: (rTop = NoReg or: [rOopTop = NoReg or: [rOopNext = NoReg]]).
+ ^ aBlock value: rTop value: rOopTop value: rOopNext
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeIntegerOop: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeIntegerOop: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rTop rOopTop topRegisterMask |
+ rTop := rOopTop := NoReg.
+ topRegisterMask := 0.
+
+ self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [
+ rTop := self ssNativeTop nativeRegisterOrNone.
+ ].
+
+ self ssTop registerOrNone ~= NoReg ifTrue: [
+ rOopTop := self ssTop registerOrNone.
+ topRegisterMask := self registerMaskFor: rOopTop.
+ ].
+
+ rTop = NoReg ifTrue: [
+ rTop := self allocateRegNotConflictingWith: topRegisterMask
+ ].
+
+ rOopTop = NoReg ifTrue: [
+ rOopTop := self allocateRegNotConflictingWith: (self registerMaskFor: rTop)
+ ].
+
+ self deny: (rTop = NoReg or: [rOopTop = NoReg]).
+ ^ aBlock value: rTop value: rOopTop
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeIntegerOopResultOop: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeIntegerOopResultOop: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rTop rOopTop rOopResult topRegisterMask |
+ rTop := rOopTop:= NoReg.
+ rOopResult := NoReg.
+ topRegisterMask := 0.
+
+ self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [
+ rTop := self ssNativeTop nativeRegisterOrNone.
+ ].
+
+ self ssTop registerOrNone ~= NoReg ifTrue: [
+ rOopTop := self ssTop registerOrNone.
+ topRegisterMask := self registerMaskFor: rOopTop.
+ ].
+
+ rTop = NoReg ifTrue: [
+ rTop := self allocateRegNotConflictingWith: topRegisterMask
+ ].
+
+ rOopTop = NoReg ifTrue: [
+ rOopTop := self allocateRegNotConflictingWith: (self registerMaskFor: rTop)
+ ].
+
+ rOopResult := self allocateRegNotConflictingWith: (self registerMaskFor: rTop and: rOopTop).
+
+ self deny: (rTop = NoReg or: [rOopTop = NoReg or: [rOopResult = NoReg]]).
+
+ ^ aBlock value: rTop value: rOopTop value: rOopResult
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeIntegerResultFloat: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeIntegerResultFloat: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rTop frResult|
+ rTop := NoReg.
+ frResult := NoReg
+
+ self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [
+ rTop := self ssNativeTop nativeRegisterOrNone.
+ ].
+
+ rTop = NoReg ifTrue:
+ [ rTop := self allocateRegNotConflictingWith: self emptyRegisterMask].
+
+ frResult := self allocateFloatRegNotConflictingWith: self emptyRegisterMask.
+
+ self deny: (rTop = NoReg or: [frResult = NoReg]).
+ ^ aBlock value: rTop value: frResult
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeIntegerResultInteger2: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeIntegerResultInteger2: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rTop rResult rResult2 |
+ rTop := NoReg.
+ rResult := rResult := NoReg
+
+ self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [
+ rTop := self ssNativeTop nativeRegisterOrNone.
+ ].
+
+ rTop = NoReg ifTrue:
+ [ rTop := self allocateRegNotConflictingWith: self emptyRegisterMask].
+
+ rResult := self allocateRegNotConflictingWith: (self registerMaskFor: rTop).
+ rResult2 := self allocateRegNotConflictingWith: (self registerMaskFor: rTop and: rResult).
+
+ self deny: (rTop = NoReg or: [rResult = NoReg or: [rResult2 = NoReg]]).
+ ^ aBlock value: rTop value: rResult value: rResult2
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeIntegerResultInteger: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeIntegerResultInteger: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rTop rResult|
+ rTop := NoReg.
+ rResult := NoReg
+
+ self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [
+ rTop := self ssNativeTop nativeRegisterOrNone.
+ ].
+
+ rTop = NoReg ifTrue:
+ [ rTop := self allocateRegNotConflictingWith: self emptyRegisterMask].
+
+ rResult := self allocateRegNotConflictingWith: (self registerMaskFor: rTop).
+
+ self deny: (rTop = NoReg or: [rResult = NoReg]).
+ ^ aBlock value: rTop value: rResult
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeIntegerResultOop: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeIntegerResultOop: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rTop rResult|
+ rTop := NoReg.
+ rResult := NoReg
+
+ self ssNativeTop nativeRegisterOrNone ~= NoReg ifTrue: [
+ rTop := self ssNativeTop nativeRegisterOrNone.
+ ].
+
+ rTop = NoReg ifTrue:
+ [ rTop := self allocateRegNotConflictingWith: self emptyRegisterMask].
+
+ rResult := self allocateRegNotConflictingWith: (self registerMaskFor: rTop).
+
+ self deny: (rTop = NoReg or: [rResult = NoReg]).
+ ^ aBlock value: rTop value: rResult
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeOop2: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeOop2: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rOopTop rOopNext oopTopRegisterMask |
+ rOopTop := rOopNext := NoReg.
+ oopTopRegisterMask := 0.
+
+ self ssTop registerOrNone ~= NoReg ifTrue: [
+ rOopTop := self ssTop registerOrNone.
+ ].
+
+ (self ssValue: 1) registerOrNone ~= NoReg ifTrue: [
+ rOopNext := (self ssValue: 1) registerOrNone.
+ oopTopRegisterMask := self registerMaskFor: rOopNext.
+ ].
+
+ rOopTop = NoReg ifTrue: [
+ rOopTop := self allocateRegNotConflictingWith: oopTopRegisterMask
+ ].
+
+ rOopNext = NoReg ifTrue: [
+ rOopNext := self allocateRegNotConflictingWith: (self registerMaskFor: rOopTop)
+ ].
+
+ self deny: (rOopTop = NoReg or: [rOopNext = NoReg ]).
+ ^ aBlock value: rOopTop value: rOopNext
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeOop2ResultInteger: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeOop2ResultInteger: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rOopTop rOopNext rResult oopTopRegisterMask |
+ rOopTop := rOopNext := NoReg.
+ rResult := NoReg.
+ oopTopRegisterMask := 0.
+
+ self ssTop registerOrNone ~= NoReg ifTrue: [
+ rOopTop := self ssTop registerOrNone.
+ ].
+
+ (self ssValue: 1) registerOrNone ~= NoReg ifTrue: [
+ rOopNext := (self ssValue: 1) registerOrNone.
+ oopTopRegisterMask := self registerMaskFor: rOopNext.
+ ].
+
+ rOopTop = NoReg ifTrue: [
+ rOopTop := self allocateRegNotConflictingWith: oopTopRegisterMask
+ ].
+
+ rOopNext = NoReg ifTrue: [
+ rOopNext := self allocateRegNotConflictingWith: (self registerMaskFor: rOopTop)
+ ].
+
+ rResult := self allocateRegNotConflictingWith: (self registerMaskFor: rOopTop and: rOopNext).
+
+ self deny: (rOopTop = NoReg or: [rOopNext = NoReg or: [rResult = NoReg]]).
+ ^ aBlock value: rOopTop value: rOopNext value: rResult
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeOop: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeOop: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rOopTop |
+ rOopTop := NoReg.
+
+ self ssTop registerOrNone ~= NoReg ifTrue: [
+ rOopTop := self ssTop registerOrNone.
+ ].
+
+ rOopTop = NoReg ifTrue: [
+ rOopTop := self allocateRegNotConflictingWith: (self emptyRegisterMask)
+ ].
+
+ self deny: (rOopTop = NoReg).
+ ^ aBlock value: rOopTop
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeOopResultFloat: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeOopResultFloat: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rOopTop frResult |
+ rOopTop := NoReg.
+ frResult := NoReg.
+
+ self ssTop registerOrNone ~= NoReg ifTrue: [
+ rOopTop := self ssTop registerOrNone.
+ ].
+
+ rOopTop = NoReg ifTrue: [
+ rOopTop := self allocateRegNotConflictingWith: (self emptyRegisterMask)
+ ].
+
+ frResult := self allocateFloatRegNotConflictingWith: (self emptyRegisterMask).
+
+ self deny: (rOopTop = NoReg or: [frResult = NoReg]).
+ ^ aBlock value: rOopTop value: frResult
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeOopResultInteger2: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeOopResultInteger2: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rOopTop rResult rResult2 |
+ rOopTop := NoReg.
+ rResult := rResult2 := NoReg.
+
+ self ssTop registerOrNone ~= NoReg ifTrue: [
+ rOopTop := self ssTop registerOrNone.
+ ].
+
+ rOopTop = NoReg ifTrue: [
+ rOopTop := self allocateRegNotConflictingWith: (self emptyRegisterMask)
+ ].
+
+ rResult := self allocateRegNotConflictingWith: (self registerMaskFor: rOopTop).
+ rResult2 := self allocateRegNotConflictingWith: (self registerMaskFor: rOopTop and: rResult).
+
+ self deny: (rOopTop = NoReg or: [rResult = NoReg]).
+ ^ aBlock value: rOopTop value: rResult value: rResult2
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeOopResultInteger: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeOopResultInteger: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rOopTop rResult |
+ rOopTop := NoReg.
+ rResult := NoReg.
+
+ self ssTop registerOrNone ~= NoReg ifTrue: [
+ rOopTop := self ssTop registerOrNone.
+ ].
+
+ rOopTop = NoReg ifTrue: [
+ rOopTop := self allocateRegNotConflictingWith: (self emptyRegisterMask)
+ ].
+
+ rResult := self allocateRegNotConflictingWith: (self registerMaskFor: rOopTop).
+
+ self deny: (rOopTop = NoReg or: [rResult = NoReg]).
+ ^ aBlock value: rOopTop value: rResult
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeOopResultOop: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeOopResultOop: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rOopTop rResult |
+ rOopTop := NoReg.
+ rResult := NoReg.
+
+ self ssTop registerOrNone ~= NoReg ifTrue: [
+ rOopTop := self ssTop registerOrNone.
+ ].
+
+ rOopTop = NoReg ifTrue: [
+ rOopTop := self allocateRegNotConflictingWith: (self emptyRegisterMask)
+ ].
+
+ rResult := self allocateRegNotConflictingWith: (self registerMaskFor: rOopTop).
+
+ self deny: (rOopTop = NoReg or: [rResult = NoReg]).
+ ^ aBlock value: rOopTop value: rResult
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeResultFloat: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeResultFloat: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | frResult |
+ frResult := NoReg.
+
+ "Float result".
+ frResult := self allocateFloatRegNotConflictingWith: (self emptyRegisterMask).
+ self deny: (frResult = NoReg).
+
+ ^ aBlock value: frResult
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeResultInteger2: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeResultInteger2: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rResult rResult2 |
+ rResult := rResult2 := NoReg.
+
+ "Float result".
+ rResult := self allocateRegNotConflictingWith: (self emptyRegisterMask).
+ rResult2 := self allocateRegNotConflictingWith: (self registerMaskFor: rResult).
+ self deny: (rResult = NoReg or: [rResult2 = NoReg]).
+
+ ^ aBlock value: rResult value: rResult2
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>allocateRegistersForLowcodeResultInteger: (in category 'inline primitive register allocation') -----
+ allocateRegistersForLowcodeResultInteger: aBlock
+ <option: #LowcodeVM>
+ <inline: true>
+
+ | rResult |
+ rResult := NoReg.
+
+ "Float result".
+ rResult := self allocateRegNotConflictingWith: (self emptyRegisterMask).
+ self deny: (rResult = NoReg).
+
+ ^ aBlock value: rResult
+ !
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>freeAnyFloatRegNotConflictingWith: (in category 'simulation stack') -----
+ freeAnyFloatRegNotConflictingWith: regMask
+ "Spill the closest register on stack not conflicting with regMask.
+ Assertion Failure if regMask has already all the registers"
+ <var: #desc type: #'CogSimStackEntry *'>
+ | reg index |
+ self assert: needsFrame.
+ reg := NoReg.
+ index := simSpillBase max: 0.
+ LowcodeVM ifTrue: [
+ index := simNativeSpillBase max: 0.
+ [reg = NoReg and: [index < simNativeStackPtr]] whileTrue:
+ [ | desc |
+ desc := self simNativeStackAt: index.
+ (desc type = SSRegisterSingleFloat or: [desc type = SSRegisterDoubleFloat]) ifTrue:
+ [(regMask anyMask: (self registerMaskFor: desc register)) ifFalse:
+ [reg := desc register]].
+ index := index + 1].
+ ].
+ self deny: reg = NoReg.
+ self ssAllocateRequiredFloatReg: reg.
+ ^reg!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeAdd32 (in category 'inline primitive generators generated code') -----
genLowcodeAdd32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second first |
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self AddR: second R: first.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeAdd64 (in category 'inline primitive generators generated code') -----
genLowcodeAdd64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | secondLow secondHigh firstHigh first second firstLow |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | secondLow firstLow secondHigh first second firstHigh |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger4: [:secondLowValue :secondHighValue :firstLowValue :firstHighValue |
+ secondLow := secondLowValue.
+ secondHigh := secondHighValue.
+ firstLow := firstLowValue.
+ firstHigh := firstHighValue.
+ ].
- (secondLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (secondLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (secondHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: secondLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (secondHigh := Arg1Reg)].
-
- (firstLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (firstLow := SendNumArgsReg)].
-
- (firstHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh)) bitOr: (self registerMaskFor: firstLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (firstHigh := ClassReg)].
- (((secondLow = ReceiverResultReg or: [secondHigh = ReceiverResultReg]) or: [firstLow = ReceiverResultReg]) or: [firstHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: secondLow secondReg: secondHigh.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: firstLow secondReg: firstHigh.
self ssNativePop: 1.
self AddR: secondLow R: firstLow.
self AddcR: secondHigh R: firstHigh.
self ssPushNativeRegister: firstLow secondRegister: firstHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self AddR: second R: first.
self ssPushNativeRegister: first.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeAlloca32 (in category 'inline primitive generators generated code') -----
genLowcodeAlloca32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| size |
+ self allocateRegistersForLowcodeInteger: [:sizeValue |
+ size := sizeValue.
+ ].
- (size := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (size := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- size = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: size.
self ssNativePop: 1.
self MoveAw: coInterpreter nativeStackPointerAddress R: TempReg.
self SubR: size R: TempReg.
self AndCq: -16 R: TempReg.
self MoveR: TempReg R: size.
self MoveR: size Aw: coInterpreter nativeStackPointerAddress.
self ssPushNativeRegister: size.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeAlloca64 (in category 'inline primitive generators generated code') -----
genLowcodeAlloca64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| sizeHigh size sizeLow |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger2: [:sizeLowValue :sizeHighValue |
+ sizeLow := sizeLowValue.
+ sizeHigh := sizeHighValue.
+ ].
- (sizeLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (sizeLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (sizeHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: sizeLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (sizeHigh := Arg1Reg)].
- (sizeLow = ReceiverResultReg or: [sizeHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: sizeLow secondReg: sizeHigh.
self ssNativePop: 1.
self SubR: sizeLow R: SPReg.
self MoveR: SPReg R: sizeLow.
self ssPushNativeRegister: sizeLow.
] ifFalse: [
+ self allocateRegistersForLowcodeInteger: [:sizeValue |
+ size := sizeValue.
+ ].
- (size := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (size := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- size = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: size.
self ssNativePop: 1.
self SubR: size R: SPReg.
self MoveR: SPReg R: size.
self ssPushNativeRegister: size.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeAnd32 (in category 'inline primitive generators generated code') -----
genLowcodeAnd32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second first |
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self AndR: second R: first.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeAnd64 (in category 'inline primitive generators generated code') -----
genLowcodeAnd64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | secondLow secondHigh firstHigh first second firstLow |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | secondLow firstLow secondHigh first second firstHigh |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger4: [:secondLowValue :secondHighValue :firstLowValue :firstHighValue |
+ secondLow := secondLowValue.
+ secondHigh := secondHighValue.
+ firstLow := firstLowValue.
+ firstHigh := firstHighValue.
+ ].
- (secondLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (secondLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (secondHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: secondLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (secondHigh := Arg1Reg)].
-
- (firstLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (firstLow := SendNumArgsReg)].
-
- (firstHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh)) bitOr: (self registerMaskFor: firstLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (firstHigh := ClassReg)].
- (((secondLow = ReceiverResultReg or: [secondHigh = ReceiverResultReg]) or: [firstLow = ReceiverResultReg]) or: [firstHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: secondLow secondReg: secondHigh.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: firstLow secondReg: firstHigh.
self ssNativePop: 1.
self AndR: secondLow R: firstLow.
self AndR: secondHigh R: firstHigh.
self ssPushNativeRegister: firstLow secondRegister: firstHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self AndR: second R: first.
self ssPushNativeRegister: first.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeArithmeticRightShift32 (in category 'inline primitive generators generated code') -----
genLowcodeArithmeticRightShift32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value shiftAmount |
+ self allocateRegistersForLowcodeInteger2: [:shiftAmountValue :valueValue |
+ shiftAmount := shiftAmountValue.
+ value := valueValue.
+ ].
- (shiftAmount := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (shiftAmount := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: shiftAmount))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (shiftAmount = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: shiftAmount.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self ArithmeticShiftRightR: shiftAmount R: value.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeArithmeticRightShift64 (in category 'inline primitive generators generated code') -----
genLowcodeArithmeticRightShift64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | value result shiftAmountHigh shiftAmount resultLow valueLow resultHigh shiftAmountLow valueHigh |
+ self allocateRegistersForLowcodeInteger2ResultInteger: [:shiftAmountValue :valueValue :resultValue |
+ shiftAmount := shiftAmountValue.
+ value := valueValue.
+ result := resultValue.
+ ].
- <option: #LowcodeVM> "Lowcode instruction generator"
- | value result shiftAmount shiftAmountHigh resultLow valueLow resultHigh shiftAmountLow valueHigh |
- (shiftAmount := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (shiftAmount := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: shiftAmount))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
-
- (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: shiftAmount)) bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (result := SendNumArgsReg)].
- ((shiftAmount = ReceiverResultReg or: [value = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: shiftAmount.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeBeginCall (in category 'inline primitive generators generated code') -----
genLowcodeBeginCall
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| alignment |
alignment := extA.
self beginHighLevelCall: alignment.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeBoolean32ToOop (in category 'inline primitive generators generated code') -----
genLowcodeBoolean32ToOop
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value inst cont object trueJump |
+ self allocateRegistersForLowcodeIntegerResultOop: [:valueValue :objectValue |
+ value := valueValue.
+ object := objectValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (object := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (object := Arg1Reg)].
- (value = ReceiverResultReg or: [object = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self CmpCq: 0 R: value.
trueJump := self JumpNonZero: 0.
"False"
self annotate: (self MoveCw: objectMemory falseObject R: value) objRef: objectMemory falseObject.
cont := self Jump: 0.
"True"
inst := self MoveCw: objectMemory trueObject R: value.
trueJump jmpTarget: inst.
self annotate: inst objRef: objectMemory trueObject.
cont jmpTarget: self Label.
self ssPushRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeBoolean64ToOop (in category 'inline primitive generators generated code') -----
genLowcodeBoolean64ToOop
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value inst trueJump2 cont valueLow object trueJump valueHigh |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger2ResultOop: [:valueLowValue :valueHighValue :objectValue |
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ object := objectValue.
+ ].
- (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (valueLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
-
- (object := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: valueLow)) bitOr: (self registerMaskFor: valueHigh))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (object := SendNumArgsReg)].
- ((valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) or: [object = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
self ssNativePop: 1.
self OrR: valueLow R: valueHigh.
trueJump := self JumpNonZero: 0.
"False"
self annotate: (self MoveCw: objectMemory falseObject R: valueLow) objRef: objectMemory falseObject.
cont := self Jump: 0.
"True"
inst := self MoveCw: objectMemory trueObject R: valueLow.
trueJump jmpTarget: inst.
self annotate: inst objRef: objectMemory trueObject.
cont jmpTarget: self Label.
self ssPushRegister: valueLow.
] ifFalse: [
+ self allocateRegistersForLowcodeIntegerResultOop: [:valueValue :objectValue |
+ value := valueValue.
+ object := objectValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (object := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (object := Arg1Reg)].
- (value = ReceiverResultReg or: [object = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self CmpCq: 0 R: value.
trueJump := self JumpNonZero: 0.
"False"
self annotate: (self MoveCw: objectMemory falseObject R: value) objRef: objectMemory falseObject.
cont := self Jump: 0.
"True"
inst := self MoveCw: objectMemory trueObject R: value.
trueJump jmpTarget: inst.
self annotate: inst objRef: objectMemory trueObject.
cont jmpTarget: self Label.
self ssPushRegister: value.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeByteSizeOf (in category 'inline primitive generators generated code') -----
genLowcodeByteSizeOf
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| object value |
+ self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue |
+ object := objectValue.
+ value := valueValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
self ssFlushAll.
objectRepresentation genLcByteSizeOf: object to: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeCallArgumentFloat32 (in category 'inline primitive generators generated code') -----
genLowcodeCallArgumentFloat32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self ssNativeTop nativeStackPopToReg: DPFPReg0.
self ssNativePop: 1.
self MoveRs: DPFPReg0 M32: BytesPerWord negated r: SPReg.
self SubCq: BytesPerWord R: SPReg.
currentCallCleanUpSize := currentCallCleanUpSize + BytesPerWord.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeCallArgumentFloat64 (in category 'inline primitive generators generated code') -----
genLowcodeCallArgumentFloat64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self ssNativeTop nativeStackPopToReg: DPFPReg0.
self ssNativePop: 1.
self MoveRd: DPFPReg0 M64: -8 r: SPReg.
self SubCq: 8 R: SPReg.
currentCallCleanUpSize := currentCallCleanUpSize + 8.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeCallArgumentInt32 (in category 'inline primitive generators generated code') -----
genLowcodeCallArgumentInt32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self ssNativeTop nativeStackPopToReg: TempReg.
self ssNativePop: 1.
self PushR: TempReg.
currentCallCleanUpSize := currentCallCleanUpSize + BytesPerWord.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeCallArgumentInt64 (in category 'inline primitive generators generated code') -----
genLowcodeCallArgumentInt64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
BytesPerWord = 4 ifTrue: [
self ssNativeTop nativeStackPopToReg: TempReg secondReg: ReceiverResultReg.
self ssNativePop: 1.
self PushR: TempReg.
self PushR: ReceiverResultReg.
currentCallCleanUpSize := currentCallCleanUpSize + 8.
] ifFalse: [
self ssNativeTop nativeStackPopToReg: TempReg.
self ssNativePop: 1.
self PushR: TempReg.
currentCallCleanUpSize := currentCallCleanUpSize + BytesPerWord.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeCallArgumentPointer (in category 'inline primitive generators generated code') -----
genLowcodeCallArgumentPointer
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self ssNativeTop nativeStackPopToReg: TempReg.
self ssNativePop: 1.
self PushR: TempReg.
currentCallCleanUpSize := currentCallCleanUpSize + BytesPerWord.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeCallArgumentSpace (in category 'inline primitive generators generated code') -----
genLowcodeCallArgumentSpace
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
"Allocate space"
self SubCq: extA R: SPReg.
currentCallCleanUpSize := currentCallCleanUpSize + extA.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeCallArgumentStructure (in category 'inline primitive generators generated code') -----
genLowcodeCallArgumentStructure
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
"Fetch the pointer"
self ssNativeTop nativeStackPopToReg: TempReg.
self ssNativePop: 1.
"Allocate space"
self SubCq: extA R: SPReg.
currentCallCleanUpSize := currentCallCleanUpSize + extA.
"Copy the structure"
backEnd genMemCopy: TempReg to: SPReg constantSize: extA.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeCallInstruction (in category 'inline primitive generators generated code') -----
genLowcodeCallInstruction
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| function |
function := extA.
self CallRT: function.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeCallPhysical (in category 'inline primitive generators generated code') -----
genLowcodeCallPhysical
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| registerID |
registerID := extA.
self CallR: registerID.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeCheckSessionIdentifier (in category 'inline primitive generators generated code') -----
genLowcodeCheckSessionIdentifier
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| expectedSession |
expectedSession := extA.
self ssPushNativeConstantInt32: (expectedSession = coInterpreter getThisSessionID ifTrue: [1] ifFalse: [0]).
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeCompareAndSwap32 (in category 'inline primitive generators generated code') -----
genLowcodeCompareAndSwap32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| newValue check oldValue value |
+ self allocateRegistersForLowcodeInteger3ResultInteger: [:newValueValue :oldValueValue :checkValue :valueValue |
+ newValue := newValueValue.
+ oldValue := oldValueValue.
+ check := checkValue.
+ value := valueValue.
+ ].
- (newValue := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (newValue := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (oldValue := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: newValue))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (oldValue := Arg1Reg)].
-
- (check := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: newValue)) bitOr: (self registerMaskFor: oldValue))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (check := SendNumArgsReg)].
-
- (value := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: newValue)) bitOr: (self registerMaskFor: oldValue)) bitOr: (self registerMaskFor: check))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := ClassReg)].
- (((newValue = ReceiverResultReg or: [oldValue = ReceiverResultReg]) or: [check = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: newValue.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: oldValue.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: check.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeDiv32 (in category 'inline primitive generators generated code') -----
genLowcodeDiv32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second first |
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self DivR: second R: first Quo: first Rem: second.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeDiv64 (in category 'inline primitive generators generated code') -----
genLowcodeDiv64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | secondLow secondHigh firstHigh result resultLow resultHigh first second firstLow |
+ self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :resultValue |
+ second := secondValue.
+ first := firstValue.
+ result := resultValue.
+ ].
- <option: #LowcodeVM> "Lowcode instruction generator"
- | secondLow firstLow secondHigh result resultLow resultHigh first second firstHigh |
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
-
- (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (result := SendNumArgsReg)].
- ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeDuplicateFloat32 (in category 'inline primitive generators generated code') -----
genLowcodeDuplicateFloat32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value dup2 |
+ self allocateRegistersForLowcodeFloatResultFloat: [:valueValue :dup2Value |
+ value := valueValue.
+ dup2 := dup2Value.
+ ].
- (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
-
- (dup2 := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (dup2 := DPFPReg1)].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self MoveRs: value Rs: dup2.
self ssPushNativeRegisterSingleFloat: value;
ssPushNativeRegisterSingleFloat: dup2.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeDuplicateFloat64 (in category 'inline primitive generators generated code') -----
genLowcodeDuplicateFloat64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value dup2 |
+ self allocateRegistersForLowcodeFloatResultFloat: [:valueValue :dup2Value |
+ value := valueValue.
+ dup2 := dup2Value.
+ ].
- (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
-
- (dup2 := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (dup2 := DPFPReg1)].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self MoveRd: value Rd: dup2.
self ssPushNativeRegisterDoubleFloat: value;
ssPushNativeRegisterDoubleFloat: dup2.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeDuplicateInt32 (in category 'inline primitive generators generated code') -----
genLowcodeDuplicateInt32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value dup2 |
+ self allocateRegistersForLowcodeIntegerResultInteger: [:valueValue :dup2Value |
+ value := valueValue.
+ dup2 := dup2Value.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (dup2 := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (dup2 := Arg1Reg)].
- (value = ReceiverResultReg or: [dup2 = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self MoveR: value R: dup2.
self ssPushNativeRegister: value;
ssPushNativeRegister: dup2.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeDuplicateInt64 (in category 'inline primitive generators generated code') -----
genLowcodeDuplicateInt64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value dup2Low dup2 valueLow dup2High valueHigh |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger2ResultInteger2: [:valueLowValue :valueHighValue :dup2LowValue :dup2HighValue |
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ dup2Low := dup2LowValue.
+ dup2High := dup2HighValue.
+ ].
- (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (valueLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
-
- (dup2Low := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: valueLow)) bitOr: (self registerMaskFor: valueHigh))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (dup2Low := SendNumArgsReg)].
-
- (dup2High := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: valueLow)) bitOr: (self registerMaskFor: valueHigh)) bitOr: (self registerMaskFor: dup2Low))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (dup2High := ClassReg)].
- (((valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) or: [dup2Low = ReceiverResultReg]) or: [dup2High = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
self ssNativePop: 1.
self MoveR: valueLow R: dup2Low.
self MoveR: valueHigh R: dup2High.
self ssPushNativeRegister: valueLow secondRegister: valueHigh.
self ssPushNativeRegister: dup2Low secondRegister: dup2High.
] ifFalse: [
+ self allocateRegistersForLowcodeIntegerResultInteger: [:valueValue :dup2Value |
+ value := valueValue.
+ dup2 := dup2Value.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (dup2 := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (dup2 := Arg1Reg)].
- (value = ReceiverResultReg or: [dup2 = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self MoveR: value R: dup2.
self ssPushNativeRegister: value.
self ssPushNativeRegister: dup2.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeDuplicatePointer (in category 'inline primitive generators generated code') -----
genLowcodeDuplicatePointer
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| dup2 pointerValue |
+ self allocateRegistersForLowcodeIntegerResultInteger: [:pointerValueValue :dup2Value |
+ pointerValue := pointerValueValue.
+ dup2 := dup2Value.
+ ].
- (pointerValue := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointerValue := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (dup2 := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointerValue))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (dup2 := Arg1Reg)].
- (pointerValue = ReceiverResultReg or: [dup2 = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointerValue.
self ssNativePop: 1.
self MoveR: pointerValue R: dup2.
self ssPushNativeRegister: pointerValue;
ssPushNativeRegister: dup2.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeEffectiveAddress32 (in category 'inline primitive generators generated code') -----
genLowcodeEffectiveAddress32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | index base offset scale |
+ self allocateRegistersForLowcodeInteger4: [:offsetValue :scaleValue :indexValue :baseValue |
+ offset := offsetValue.
+ scale := scaleValue.
+ index := indexValue.
+ base := baseValue.
+ ].
- <option: #LowcodeVM> "Lowcode instruction generator"
- | offset base index scale |
- (offset := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (offset := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (scale := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: offset))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (scale := Arg1Reg)].
-
- (index := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: offset)) bitOr: (self registerMaskFor: scale))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (index := SendNumArgsReg)].
-
- (base := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: offset)) bitOr: (self registerMaskFor: scale)) bitOr: (self registerMaskFor: index))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (base := ClassReg)].
- (((offset = ReceiverResultReg or: [scale = ReceiverResultReg]) or: [index = ReceiverResultReg]) or: [base = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: offset.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: scale.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: index.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: base.
self ssNativePop: 1.
self MulR: scale R: index.
self AddR: index R: base.
self AddR: offset R: base.
self ssPushNativeRegister: base.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeEffectiveAddress64 (in category 'inline primitive generators generated code') -----
genLowcodeEffectiveAddress64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| base index indexLow indexHigh scaleHigh offsetLow scaleLow offset offsetHigh result scale |
+ self allocateRegistersForLowcodeInteger4ResultInteger: [:offsetValue :scaleValue :indexValue :baseValue :resultValue |
+ offset := offsetValue.
+ scale := scaleValue.
+ index := indexValue.
+ base := baseValue.
+ result := resultValue.
+ ].
- (offset := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (offset := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (scale := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: offset))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (scale := Arg1Reg)].
-
- (index := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: offset)) bitOr: (self registerMaskFor: scale))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (index := SendNumArgsReg)].
-
- (base := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: offset)) bitOr: (self registerMaskFor: scale)) bitOr: (self registerMaskFor: index))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (base := ClassReg)].
-
- (result := backEnd availableRegisterOrNoneFor: ((((self liveRegisters bitOr: (self registerMaskFor: offset)) bitOr: (self registerMaskFor: scale)) bitOr: (self registerMaskFor: index)) bitOr: (self registerMaskFor: base))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (result := ReceiverResultReg)].
- ((((offset = ReceiverResultReg or: [scale = ReceiverResultReg]) or: [index = ReceiverResultReg]) or: [base = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: offset.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: scale.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: index.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: base.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeEndCall (in category 'inline primitive generators generated code') -----
genLowcodeEndCall
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self endHighLevelCallWithCleanup.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeEndCallNoCleanup (in category 'inline primitive generators generated code') -----
genLowcodeEndCallNoCleanup
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self endHighLevelCallWithoutCleanup.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFirstFieldPointer (in category 'inline primitive generators generated code') -----
genLowcodeFirstFieldPointer
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| object |
+ self allocateRegistersForLowcodeOop: [:objectValue |
+ object := objectValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- object = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
objectRepresentation genLcFirstFieldPointer: object.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFirstIndexableFieldPointer (in category 'inline primitive generators generated code') -----
genLowcodeFirstIndexableFieldPointer
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| object |
+ self allocateRegistersForLowcodeOop: [:objectValue |
+ object := objectValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- object = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
objectRepresentation genLcFirstIndexableFieldPointer: object.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Add (in category 'inline primitive generators generated code') -----
genLowcodeFloat32Add
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second first |
+ self allocateRegistersForLowcodeFloat2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
-
- (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self AddRs: second Rs: first.
self ssPushNativeRegisterSingleFloat: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Div (in category 'inline primitive generators generated code') -----
genLowcodeFloat32Div
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second first |
+ self allocateRegistersForLowcodeFloat2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
-
- (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self DivRs: second Rs: first.
self ssPushNativeRegisterSingleFloat: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Equal (in category 'inline primitive generators generated code') -----
genLowcodeFloat32Equal
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value contJump falseJump first second |
+ self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue |
+ second := secondValue.
+ first := firstValue.
+ value := valueValue.
+ ].
- (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
-
- (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
-
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpRs: second Rs: first.
falseJump := self JumpFPNotEqual: 0.
"True result"
self MoveCq: 1 R: value.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: value.
contJump jmpTarget: self Label.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Great (in category 'inline primitive generators generated code') -----
genLowcodeFloat32Great
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value contJump falseJump first second |
+ self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue |
+ second := secondValue.
+ first := firstValue.
+ value := valueValue.
+ ].
- (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
-
- (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
-
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpRs: second Rs: first.
falseJump := self JumpFPLessOrEqual: 0.
"True result"
self MoveCq: 1 R: value.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: value.
contJump jmpTarget: self Label.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32GreatEqual (in category 'inline primitive generators generated code') -----
genLowcodeFloat32GreatEqual
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value contJump falseJump first second |
+ self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue |
+ second := secondValue.
+ first := firstValue.
+ value := valueValue.
+ ].
- (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
-
- (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
-
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpRs: second Rs: first.
falseJump := self JumpFPLess: 0.
"True result"
self MoveCq: 1 R: value.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: value.
contJump jmpTarget: self Label.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Less (in category 'inline primitive generators generated code') -----
genLowcodeFloat32Less
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value contJump falseJump first second |
+ self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue |
+ second := secondValue.
+ first := firstValue.
+ value := valueValue.
+ ].
- (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
-
- (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
-
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpRs: second Rs: first.
falseJump := self JumpFPGreaterOrEqual: 0.
"True result"
self MoveCq: 1 R: value.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: value.
contJump jmpTarget: self Label.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32LessEqual (in category 'inline primitive generators generated code') -----
genLowcodeFloat32LessEqual
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value contJump falseJump first second |
+ self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue |
+ second := secondValue.
+ first := firstValue.
+ value := valueValue.
+ ].
- (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
-
- (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
-
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpRs: second Rs: first.
falseJump := self JumpFPGreater: 0.
"True result"
self MoveCq: 1 R: value.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: value.
contJump jmpTarget: self Label.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Mul (in category 'inline primitive generators generated code') -----
genLowcodeFloat32Mul
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second first |
+ self allocateRegistersForLowcodeFloat2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
-
- (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self MulRs: second Rs: first.
self ssPushNativeRegisterSingleFloat: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Neg (in category 'inline primitive generators generated code') -----
genLowcodeFloat32Neg
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value result |
+ self allocateRegistersForLowcodeFloatResultFloat: [:valueValue :resultValue |
+ value := valueValue.
+ result := resultValue.
+ ].
- (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
-
- (result := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (result := DPFPReg1)].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self XorRs: result Rs: result.
self SubRs: value Rs: result.
self ssPushNativeRegisterSingleFloat: result.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32NotEqual (in category 'inline primitive generators generated code') -----
genLowcodeFloat32NotEqual
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value contJump falseJump first second |
+ self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue |
+ second := secondValue.
+ first := firstValue.
+ value := valueValue.
+ ].
- (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
-
- (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
-
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpRs: second Rs: first.
falseJump := self JumpFPEqual: 0.
"True result"
self MoveCq: 1 R: value.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: value.
contJump jmpTarget: self Label.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Sqrt (in category 'inline primitive generators generated code') -----
genLowcodeFloat32Sqrt
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value |
+ self allocateRegistersForLowcodeFloat: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self SqrtRs: value.
self ssPushNativeRegisterSingleFloat: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32Sub (in category 'inline primitive generators generated code') -----
genLowcodeFloat32Sub
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second first |
+ self allocateRegistersForLowcodeFloat2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
-
- (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self SubRs: second Rs: first.
self ssPushNativeRegisterSingleFloat: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32ToFloat64 (in category 'inline primitive generators generated code') -----
genLowcodeFloat32ToFloat64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| singleFloatValue |
+ self allocateRegistersForLowcodeFloat: [:singleFloatValueValue |
+ singleFloatValue := singleFloatValueValue.
+ ].
- (singleFloatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (singleFloatValue := DPFPReg0)].
self ssNativeTop nativePopToReg: singleFloatValue.
self ssNativePop: 1.
self ConvertRs: singleFloatValue Rd: singleFloatValue.
self ssPushNativeRegisterDoubleFloat: singleFloatValue.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32ToInt32 (in category 'inline primitive generators generated code') -----
genLowcodeFloat32ToInt32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value result |
+ self allocateRegistersForLowcodeFloatResultInteger: [:valueValue :resultValue |
+ value := valueValue.
+ result := resultValue.
+ ].
- (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
-
- (result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (result := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- result = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self ConvertRs: value R: result.
self ssPushNativeRegister: result.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32ToInt64 (in category 'inline primitive generators generated code') -----
genLowcodeFloat32ToInt64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| resultLow resultHigh value result |
+ self allocateRegistersForLowcodeFloatResultInteger: [:valueValue :resultValue |
+ value := valueValue.
+ result := resultValue.
+ ].
- (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
-
- (result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (result := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- result = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32ToOop (in category 'inline primitive generators generated code') -----
genLowcodeFloat32ToOop
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| singleFloatValue object |
+ self allocateRegistersForLowcodeFloatResultOop: [:singleFloatValueValue :objectValue |
+ singleFloatValue := singleFloatValueValue.
+ object := objectValue.
+ ].
- (singleFloatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (singleFloatValue := DPFPReg0)].
-
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- object = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: singleFloatValue.
self ssNativePop: 1.
self ssFlushAll.
objectRepresentation genLcFloat32: singleFloatValue toOop: object.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32ToUInt32 (in category 'inline primitive generators generated code') -----
genLowcodeFloat32ToUInt32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value result |
+ self allocateRegistersForLowcodeFloatResultInteger: [:valueValue :resultValue |
+ value := valueValue.
+ result := resultValue.
+ ].
- (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
-
- (result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (result := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- result = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self ConvertRs: value R: result.
self ssPushNativeRegister: result.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat32ToUInt64 (in category 'inline primitive generators generated code') -----
genLowcodeFloat32ToUInt64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| resultLow resultHigh value result |
+ self allocateRegistersForLowcodeFloatResultInteger: [:valueValue :resultValue |
+ value := valueValue.
+ result := resultValue.
+ ].
- (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
-
- (result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (result := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- result = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Add (in category 'inline primitive generators generated code') -----
genLowcodeFloat64Add
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second first |
+ self allocateRegistersForLowcodeFloat2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
-
- (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self AddRd: second Rd: first.
self ssPushNativeRegisterDoubleFloat: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Div (in category 'inline primitive generators generated code') -----
genLowcodeFloat64Div
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second first |
+ self allocateRegistersForLowcodeFloat2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
-
- (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self DivRd: second Rd: first.
self ssPushNativeRegisterDoubleFloat: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Equal (in category 'inline primitive generators generated code') -----
genLowcodeFloat64Equal
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value contJump falseJump first second |
+ self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue |
+ second := secondValue.
+ first := firstValue.
+ value := valueValue.
+ ].
- (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
-
- (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
-
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpRd: second Rd: first.
falseJump := self JumpFPNotEqual: 0.
"True result"
self MoveCq: 1 R: value.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: value.
contJump jmpTarget: self Label.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Great (in category 'inline primitive generators generated code') -----
genLowcodeFloat64Great
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value contJump falseJump first second |
+ self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue |
+ second := secondValue.
+ first := firstValue.
+ value := valueValue.
+ ].
- (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
-
- (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
-
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpRd: second Rd: first.
falseJump := self JumpFPLessOrEqual: 0.
"True result"
self MoveCq: 1 R: value.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: value.
contJump jmpTarget: self Label.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64GreatEqual (in category 'inline primitive generators generated code') -----
genLowcodeFloat64GreatEqual
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value contJump falseJump first second |
+ self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue |
+ second := secondValue.
+ first := firstValue.
+ value := valueValue.
+ ].
- (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
-
- (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
-
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpRd: second Rd: first.
falseJump := self JumpFPLess: 0.
"True result"
self MoveCq: 1 R: value.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: value.
contJump jmpTarget: self Label.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Less (in category 'inline primitive generators generated code') -----
genLowcodeFloat64Less
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value contJump falseJump first second |
+ self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue |
+ second := secondValue.
+ first := firstValue.
+ value := valueValue.
+ ].
- (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
-
- (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
-
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpRd: second Rd: first.
falseJump := self JumpFPGreaterOrEqual: 0.
"True result"
self MoveCq: 1 R: value.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: value.
contJump jmpTarget: self Label.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64LessEqual (in category 'inline primitive generators generated code') -----
genLowcodeFloat64LessEqual
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value contJump falseJump first second |
+ self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue |
+ second := secondValue.
+ first := firstValue.
+ value := valueValue.
+ ].
- (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
-
- (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
-
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpRd: second Rd: first.
falseJump := self JumpFPGreater: 0.
"True result"
self MoveCq: 1 R: value.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: value.
contJump jmpTarget: self Label.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Mul (in category 'inline primitive generators generated code') -----
genLowcodeFloat64Mul
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second first |
+ self allocateRegistersForLowcodeFloat2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
-
- (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self MulRd: second Rd: first.
self ssPushNativeRegisterDoubleFloat: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Neg (in category 'inline primitive generators generated code') -----
genLowcodeFloat64Neg
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value result |
+ self allocateRegistersForLowcodeFloatResultFloat: [:valueValue :resultValue |
+ value := valueValue.
+ result := resultValue.
+ ].
- (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
-
- (result := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (result := DPFPReg1)].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self XorRd: result Rd: result.
self SubRd: value Rd: result.
self ssPushNativeRegisterDoubleFloat: result.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64NotEqual (in category 'inline primitive generators generated code') -----
genLowcodeFloat64NotEqual
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value contJump falseJump first second |
+ self allocateRegistersForLowcodeFloat2ResultInteger: [:secondValue :firstValue :valueValue |
+ second := secondValue.
+ first := firstValue.
+ value := valueValue.
+ ].
- (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
-
- (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
-
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpRd: second Rd: first.
falseJump := self JumpFPEqual: 0.
"True result"
self MoveCq: 1 R: value.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: value.
contJump jmpTarget: self Label.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Sqrt (in category 'inline primitive generators generated code') -----
genLowcodeFloat64Sqrt
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value |
+ self allocateRegistersForLowcodeFloat: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self SqrtRd: value.
self ssPushNativeRegisterDoubleFloat: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64Sub (in category 'inline primitive generators generated code') -----
genLowcodeFloat64Sub
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second first |
+ self allocateRegistersForLowcodeFloat2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (second := DPFPReg0)].
-
- (first := backEnd availableFloatRegisterOrNoneFor: (self liveFloatRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (first := DPFPReg1)].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self SubRd: second Rd: first.
self ssPushNativeRegisterDoubleFloat: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64ToFloat32 (in category 'inline primitive generators generated code') -----
genLowcodeFloat64ToFloat32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| floatValue |
+ self allocateRegistersForLowcodeFloat: [:floatValueValue |
+ floatValue := floatValueValue.
+ ].
- (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)].
self ssNativeTop nativePopToReg: floatValue.
self ssNativePop: 1.
self ConvertRd: floatValue Rs: floatValue.
self ssPushNativeRegisterSingleFloat: floatValue.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64ToInt32 (in category 'inline primitive generators generated code') -----
genLowcodeFloat64ToInt32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| floatValue int32Result |
+ self allocateRegistersForLowcodeFloatResultInteger: [:floatValueValue :int32ResultValue |
+ floatValue := floatValueValue.
+ int32Result := int32ResultValue.
+ ].
- (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)].
-
- (int32Result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (int32Result := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- int32Result = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: floatValue.
self ssNativePop: 1.
self ConvertRd: floatValue R: int32Result.
self ssPushNativeRegister: int32Result.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64ToInt64 (in category 'inline primitive generators generated code') -----
genLowcodeFloat64ToInt64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| floatValue int64ResultLow int64Result int64ResultHigh |
+ self allocateRegistersForLowcodeFloatResultInteger: [:floatValueValue :int64ResultValue |
+ floatValue := floatValueValue.
+ int64Result := int64ResultValue.
+ ].
- (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)].
-
- (int64Result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (int64Result := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- int64Result = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: floatValue.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64ToOop (in category 'inline primitive generators generated code') -----
genLowcodeFloat64ToOop
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| floatValue object |
+ self allocateRegistersForLowcodeFloatResultOop: [:floatValueValue :objectValue |
+ floatValue := floatValueValue.
+ object := objectValue.
+ ].
- (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)].
-
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- object = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: floatValue.
self ssNativePop: 1.
self ssFlushAll.
objectRepresentation genLcFloat64: floatValue toOop: object.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64ToUInt32 (in category 'inline primitive generators generated code') -----
genLowcodeFloat64ToUInt32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| floatValue int64Result |
+ self allocateRegistersForLowcodeFloatResultInteger: [:floatValueValue :int64ResultValue |
+ floatValue := floatValueValue.
+ int64Result := int64ResultValue.
+ ].
- (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)].
-
- (int64Result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (int64Result := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- int64Result = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: floatValue.
self ssNativePop: 1.
self ConvertRd: floatValue R: int64Result.
self ssPushNativeRegister: int64Result.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFloat64ToUInt64 (in category 'inline primitive generators generated code') -----
genLowcodeFloat64ToUInt64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| floatValue int64ResultLow int64Result int64ResultHigh |
+ self allocateRegistersForLowcodeFloatResultInteger: [:floatValueValue :int64ResultValue |
+ floatValue := floatValueValue.
+ int64Result := int64ResultValue.
+ ].
- (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)].
-
- (int64Result := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (int64Result := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- int64Result = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: floatValue.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeFree (in category 'inline primitive generators generated code') -----
genLowcodeFree
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| pointer |
+ self allocateRegistersForLowcodeInteger: [:pointerValue |
+ pointer := pointerValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- pointer = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
self ssFlushAll.
pointer ~= ReceiverResultReg ifTrue: [self MoveR: pointer R: ReceiverResultReg ].
self CallRT: ceFreeTrampoline.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeInstantiateIndexable32Oop (in category 'inline primitive generators generated code') -----
genLowcodeInstantiateIndexable32Oop
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| indexableSize object classOop |
+ self allocateRegistersForLowcodeIntegerOopResultOop: [:indexableSizeValue :classOopValue :objectValue |
+ indexableSize := indexableSizeValue.
+ classOop := classOopValue.
+ object := objectValue.
+ ].
- (indexableSize := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (indexableSize := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (classOop := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: indexableSize))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (classOop := Arg1Reg)].
-
- (object := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: indexableSize)) bitOr: (self registerMaskFor: classOop))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (object := SendNumArgsReg)].
- ((indexableSize = ReceiverResultReg or: [classOop = ReceiverResultReg]) or: [object = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: indexableSize.
self ssNativePop: 1.
self ssTop popToReg: classOop.
self ssPop: 1.
self ssFlushAll.
objectRepresentation genLcInstantiateOop: classOop indexableSize: indexableSize.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeInstantiateIndexableOop (in category 'inline primitive generators generated code') -----
genLowcodeInstantiateIndexableOop
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| indexableSize object classOop |
indexableSize := extA.
+ self allocateRegistersForLowcodeOopResultOop: [:classOopValue :objectValue |
+ classOop := classOopValue.
+ object := objectValue.
+ ].
- (classOop := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (classOop := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (object := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: classOop))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (object := Arg1Reg)].
- (classOop = ReceiverResultReg or: [object = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: classOop.
self ssPop: 1.
self ssFlushAll.
objectRepresentation genLcInstantiateOop: classOop constantIndexableSize: indexableSize.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeInstantiateOop (in category 'inline primitive generators generated code') -----
genLowcodeInstantiateOop
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| classOop |
+ self allocateRegistersForLowcodeOop: [:classOopValue |
+ classOop := classOopValue.
+ ].
- (classOop := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (classOop := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- classOop = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: classOop.
self ssPop: 1.
self ssFlushAll.
objectRepresentation genLcInstantiateOop: classOop.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeInt32Equal (in category 'inline primitive generators generated code') -----
genLowcodeInt32Equal
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second falseJump contJump first |
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpR: second R: first.
falseJump := self JumpNonZero: 0.
"True result"
self MoveCq: 1 R: first.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: first.
contJump jmpTarget: self Label.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeInt32Great (in category 'inline primitive generators generated code') -----
genLowcodeInt32Great
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second falseJump contJump first |
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpR: second R: first.
falseJump := self JumpLessOrEqual: 0.
"True result"
self MoveCq: 1 R: first.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: first.
contJump jmpTarget: self Label.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeInt32GreatEqual (in category 'inline primitive generators generated code') -----
genLowcodeInt32GreatEqual
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second falseJump contJump first |
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpR: second R: first.
falseJump := self JumpLess: 0.
"True result"
self MoveCq: 1 R: first.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: first.
contJump jmpTarget: self Label.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeInt32Less (in category 'inline primitive generators generated code') -----
genLowcodeInt32Less
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second falseJump contJump first |
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpR: second R: first.
falseJump := self JumpGreaterOrEqual: 0.
"True result"
self MoveCq: 1 R: first.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: first.
contJump jmpTarget: self Label.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeInt32LessEqual (in category 'inline primitive generators generated code') -----
genLowcodeInt32LessEqual
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second falseJump contJump first |
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpR: second R: first.
falseJump := self JumpGreater: 0.
"True result"
self MoveCq: 1 R: first.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: first.
contJump jmpTarget: self Label.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeInt32NotEqual (in category 'inline primitive generators generated code') -----
genLowcodeInt32NotEqual
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second falseJump contJump first |
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpR: second R: first.
falseJump := self JumpZero: 0.
"True result"
self MoveCq: 1 R: first.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: first.
contJump jmpTarget: self Label.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeInt32ToFloat32 (in category 'inline primitive generators generated code') -----
genLowcodeInt32ToFloat32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value result |
+ self allocateRegistersForLowcodeIntegerResultFloat: [:valueValue :resultValue |
+ value := valueValue.
+ result := resultValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (result := DPFPReg0)].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self ConvertR: value Rs: result.
self ssPushNativeRegisterSingleFloat: result.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeInt32ToFloat64 (in category 'inline primitive generators generated code') -----
genLowcodeInt32ToFloat64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value result |
+ self allocateRegistersForLowcodeIntegerResultFloat: [:valueValue :resultValue |
+ value := valueValue.
+ result := resultValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (result := DPFPReg0)].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self ConvertR: value Rd: result.
self ssPushNativeRegisterDoubleFloat: result.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeInt32ToOop (in category 'inline primitive generators generated code') -----
genLowcodeInt32ToOop
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value |
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self ssFlushAll.
objectRepresentation genLcInt32ToOop: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeInt32ToPointer (in category 'inline primitive generators generated code') -----
genLowcodeInt32ToPointer
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value |
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
"TODO: Perform a NOP here"
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeInt64Equal (in category 'inline primitive generators generated code') -----
genLowcodeInt64Equal
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| falseLabel first contJump falseJump secondLow secondHigh second falseJump2 firstHigh firstLow |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger4: [:secondLowValue :secondHighValue :firstLowValue :firstHighValue |
+ secondLow := secondLowValue.
+ secondHigh := secondHighValue.
+ firstLow := firstLowValue.
+ firstHigh := firstHighValue.
+ ].
- (secondLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (secondLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (secondHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: secondLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (secondHigh := Arg1Reg)].
-
- (firstLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (firstLow := SendNumArgsReg)].
-
- (firstHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh)) bitOr: (self registerMaskFor: firstLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (firstHigh := ClassReg)].
- (((secondLow = ReceiverResultReg or: [secondHigh = ReceiverResultReg]) or: [firstLow = ReceiverResultReg]) or: [firstHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: secondLow secondReg: secondHigh.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: firstLow secondReg: firstHigh.
self ssNativePop: 1.
self CmpR: secondHigh R: firstHigh.
falseJump := self JumpNonZero: 0.
self CmpR: secondLow R: firstLow.
falseJump2 := self JumpNonZero: 0.
"True result"
self MoveCq: 1 R: firstLow.
contJump := self Jump: 0.
"False result"
falseLabel := self MoveCq: 0 R: firstLow.
falseJump jmpTarget: falseLabel.
falseJump2 jmpTarget: falseLabel.
contJump jmpTarget: self Label.
self ssPushNativeRegister: firstLow.
] ifFalse: [
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpR: second R: first.
falseJump := self JumpNonZero: 0.
"True result"
self MoveCq: 1 R: first.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: first.
contJump jmpTarget: self Label.
self ssPushNativeRegister: first.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeInt64Great (in category 'inline primitive generators generated code') -----
genLowcodeInt64Great
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | secondLow secondHigh firstHigh value first second firstLow |
+ self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :valueValue |
+ second := secondValue.
+ first := firstValue.
+ value := valueValue.
+ ].
- <option: #LowcodeVM> "Lowcode instruction generator"
- | secondLow firstLow secondHigh value first second firstHigh |
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
-
- (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := SendNumArgsReg)].
- ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeInt64GreatEqual (in category 'inline primitive generators generated code') -----
genLowcodeInt64GreatEqual
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | secondLow secondHigh firstHigh value first second firstLow |
+ self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :valueValue |
+ second := secondValue.
+ first := firstValue.
+ value := valueValue.
+ ].
- <option: #LowcodeVM> "Lowcode instruction generator"
- | secondLow firstLow secondHigh value first second firstHigh |
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
-
- (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := SendNumArgsReg)].
- ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeInt64Less (in category 'inline primitive generators generated code') -----
genLowcodeInt64Less
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | secondLow secondHigh firstHigh value first second firstLow |
+ self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :valueValue |
+ second := secondValue.
+ first := firstValue.
+ value := valueValue.
+ ].
- <option: #LowcodeVM> "Lowcode instruction generator"
- | secondLow firstLow secondHigh value first second firstHigh |
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
-
- (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := SendNumArgsReg)].
- ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeInt64LessEqual (in category 'inline primitive generators generated code') -----
genLowcodeInt64LessEqual
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | secondLow secondHigh firstHigh value first second firstLow |
+ self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :valueValue |
+ second := secondValue.
+ first := firstValue.
+ value := valueValue.
+ ].
- <option: #LowcodeVM> "Lowcode instruction generator"
- | secondLow firstLow secondHigh value first second firstHigh |
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
-
- (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := SendNumArgsReg)].
- ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeInt64NotEqual (in category 'inline primitive generators generated code') -----
genLowcodeInt64NotEqual
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| falseLabel first contJump falseJump secondLow secondHigh second falseJump2 firstHigh firstLow |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger4: [:secondLowValue :secondHighValue :firstLowValue :firstHighValue |
+ secondLow := secondLowValue.
+ secondHigh := secondHighValue.
+ firstLow := firstLowValue.
+ firstHigh := firstHighValue.
+ ].
- (secondLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (secondLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (secondHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: secondLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (secondHigh := Arg1Reg)].
-
- (firstLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (firstLow := SendNumArgsReg)].
-
- (firstHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh)) bitOr: (self registerMaskFor: firstLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (firstHigh := ClassReg)].
- (((secondLow = ReceiverResultReg or: [secondHigh = ReceiverResultReg]) or: [firstLow = ReceiverResultReg]) or: [firstHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: secondLow secondReg: secondHigh.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: firstLow secondReg: firstHigh.
self ssNativePop: 1.
self CmpR: secondHigh R: firstHigh.
falseJump := self JumpNonZero: 0.
self CmpR: secondLow R: firstLow.
falseJump2 := self JumpNonZero: 0.
"False result"
self MoveCq: 0 R: firstLow.
contJump := self Jump: 0.
"True result"
falseLabel := self MoveCq: 1 R: firstLow.
falseJump jmpTarget: falseLabel.
falseJump2 jmpTarget: falseLabel.
contJump jmpTarget: self Label.
self ssPushNativeRegister: firstLow.
] ifFalse: [
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpR: second R: first.
falseJump := self JumpZero: 0.
"True result"
self MoveCq: 1 R: first.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: first.
contJump jmpTarget: self Label.
self ssPushNativeRegister: first.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeInt64ToFloat32 (in category 'inline primitive generators generated code') -----
genLowcodeInt64ToFloat32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| valueHigh value valueLow result |
+ self allocateRegistersForLowcodeIntegerResultFloat: [:valueValue :resultValue |
+ value := valueValue.
+ result := resultValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (result := DPFPReg0)].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeInt64ToFloat64 (in category 'inline primitive generators generated code') -----
genLowcodeInt64ToFloat64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| valueHigh value valueLow result |
+ self allocateRegistersForLowcodeIntegerResultFloat: [:valueValue :resultValue |
+ value := valueValue.
+ result := resultValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (result := DPFPReg0)].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeInt64ToOop (in category 'inline primitive generators generated code') -----
genLowcodeInt64ToOop
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| valueHigh value valueLow |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger2: [:valueLowValue :valueHighValue |
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ ].
- (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (valueLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
- (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
self ssNativePop: 1.
self ssFlushAll.
objectRepresentation genLcInt64ToOop: valueLow highPart: valueHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self ssFlushAll.
objectRepresentation genLcInt64ToOop: value.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeInt64ToPointer (in category 'inline primitive generators generated code') -----
genLowcodeInt64ToPointer
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| valueHigh value valueLow |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger2: [:valueLowValue :valueHighValue |
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ ].
- (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (valueLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
- (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
self ssNativePop: 1.
self ssPushNativeRegister: valueLow.
] ifFalse: [
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self ssPushNativeRegister: value.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeIsBytes (in category 'inline primitive generators generated code') -----
genLowcodeIsBytes
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| object value |
+ self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue |
+ object := objectValue.
+ value := valueValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
objectRepresentation genLcIsBytes: object to: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeIsFloatObject (in category 'inline primitive generators generated code') -----
genLowcodeIsFloatObject
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| object value |
+ self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue |
+ object := objectValue.
+ value := valueValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
objectRepresentation genLcIsFloatObject: object to: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeIsIndexable (in category 'inline primitive generators generated code') -----
genLowcodeIsIndexable
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| object value |
+ self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue |
+ object := objectValue.
+ value := valueValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
objectRepresentation genLcIsIndexable: object to: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeIsIntegerObject (in category 'inline primitive generators generated code') -----
genLowcodeIsIntegerObject
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| object value |
+ self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue |
+ object := objectValue.
+ value := valueValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
objectRepresentation genLcIsIntegerObject: object to: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeIsPointers (in category 'inline primitive generators generated code') -----
genLowcodeIsPointers
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| object value |
+ self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue |
+ object := objectValue.
+ value := valueValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
objectRepresentation genLcIsPointers: object to: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeIsWords (in category 'inline primitive generators generated code') -----
genLowcodeIsWords
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| object value |
+ self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue |
+ object := objectValue.
+ value := valueValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
objectRepresentation genLcIsWords: object to: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeIsWordsOrBytes (in category 'inline primitive generators generated code') -----
genLowcodeIsWordsOrBytes
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| object value |
+ self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue |
+ object := objectValue.
+ value := valueValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
objectRepresentation genLcIsWordsOrBytes: object to: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLeftShift32 (in category 'inline primitive generators generated code') -----
genLowcodeLeftShift32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value shiftAmount |
+ self allocateRegistersForLowcodeInteger2: [:shiftAmountValue :valueValue |
+ shiftAmount := shiftAmountValue.
+ value := valueValue.
+ ].
- (shiftAmount := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (shiftAmount := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: shiftAmount))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (shiftAmount = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: shiftAmount.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self LogicalShiftLeftR: shiftAmount R: value.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLeftShift64 (in category 'inline primitive generators generated code') -----
genLowcodeLeftShift64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | value result shiftAmountHigh shiftAmount resultLow valueLow resultHigh shiftAmountLow valueHigh |
+ self allocateRegistersForLowcodeInteger2ResultInteger: [:shiftAmountValue :valueValue :resultValue |
+ shiftAmount := shiftAmountValue.
+ value := valueValue.
+ result := resultValue.
+ ].
- <option: #LowcodeVM> "Lowcode instruction generator"
- | value result shiftAmount shiftAmountHigh resultLow valueLow resultHigh shiftAmountLow valueHigh |
- (shiftAmount := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (shiftAmount := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: shiftAmount))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
-
- (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: shiftAmount)) bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (result := SendNumArgsReg)].
- ((shiftAmount = ReceiverResultReg or: [value = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: shiftAmount.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentAddress (in category 'inline primitive generators generated code') -----
genLowcodeLoadArgumentAddress
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | pointer baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset pointer |
baseOffset := extA.
+ self allocateRegistersForLowcodeResultInteger: [:pointerValue |
+ pointer := pointerValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- pointer = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self loadNativeArgumentAddress: baseOffset to: pointer.
self ssPushNativeRegister: pointer.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentFloat32 (in category 'inline primitive generators generated code') -----
genLowcodeLoadArgumentFloat32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | floatValue baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset floatValue |
baseOffset := extA.
+ self allocateRegistersForLowcodeResultFloat: [:floatValueValue |
+ floatValue := floatValueValue.
+ ].
- (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)].
self loadNativeArgumentAddress: baseOffset to: TempReg.
self MoveM32: 0 r: TempReg Rs: floatValue.
self ssPushNativeRegisterSingleFloat: floatValue.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentFloat64 (in category 'inline primitive generators generated code') -----
genLowcodeLoadArgumentFloat64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | doubleValue baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset doubleValue |
baseOffset := extA.
+ self allocateRegistersForLowcodeResultFloat: [:doubleValueValue |
+ doubleValue := doubleValueValue.
+ ].
- (doubleValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (doubleValue := DPFPReg0)].
self loadNativeArgumentAddress: baseOffset to: TempReg.
self MoveM64: 0 r: TempReg Rd: doubleValue.
self ssPushNativeRegisterDoubleFloat: doubleValue.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentInt16 (in category 'inline primitive generators generated code') -----
genLowcodeLoadArgumentInt16
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | value baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset value |
baseOffset := extA.
+ self allocateRegistersForLowcodeResultInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self loadNativeArgumentAddress: baseOffset to: TempReg.
self MoveM16: 0 r: TempReg R: value.
self SignExtend16R: value R: value.
self ssPushNativeRegister: value.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentInt32 (in category 'inline primitive generators generated code') -----
genLowcodeLoadArgumentInt32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | value baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset value |
baseOffset := extA.
+ self allocateRegistersForLowcodeResultInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self loadNativeArgumentAddress: baseOffset to: TempReg.
self MoveM32: 0 r: TempReg R: value.
self ssPushNativeRegister: value.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentInt64 (in category 'inline primitive generators generated code') -----
genLowcodeLoadArgumentInt64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | valueHigh value valueLow baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset value valueLow valueHigh |
baseOffset := extA.
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeResultInteger2: [:valueLowValue :valueHighValue |
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ ].
- (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (valueLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
- (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
-
"TODO: Check the endianness"
self loadNativeArgumentAddress: baseOffset to: TempReg.
self MoveM32: 0 r: TempReg R: valueLow.
self MoveM32: 4 r: TempReg R: valueHigh.
self ssPushNativeRegister: valueLow secondRegister: valueHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeResultInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self loadNativeArgumentAddress: baseOffset to: TempReg.
self MoveM64: 0 r: TempReg R: value.
self ssPushNativeRegister: value.
].
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentInt8 (in category 'inline primitive generators generated code') -----
genLowcodeLoadArgumentInt8
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | value baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset value |
baseOffset := extA.
+ self allocateRegistersForLowcodeResultInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self loadNativeArgumentAddress: baseOffset to: TempReg.
self MoveM8: 0 r: TempReg R: value.
self SignExtend8R: value R: value.
self ssPushNativeRegister: value.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentPointer (in category 'inline primitive generators generated code') -----
genLowcodeLoadArgumentPointer
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | pointerResult baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset pointerResult |
baseOffset := extA.
+ self allocateRegistersForLowcodeResultInteger: [:pointerResultValue |
+ pointerResult := pointerResultValue.
+ ].
- (pointerResult := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointerResult := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- pointerResult = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self loadNativeArgumentAddress: baseOffset to: TempReg.
self MoveMw: 0 r: TempReg R: pointerResult.
self ssPushNativeRegister: pointerResult.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentUInt16 (in category 'inline primitive generators generated code') -----
genLowcodeLoadArgumentUInt16
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | value baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset value |
baseOffset := extA.
+ self allocateRegistersForLowcodeResultInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self loadNativeArgumentAddress: baseOffset to: TempReg.
self MoveM16: 0 r: TempReg R: value.
self ssPushNativeRegister: value.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentUInt32 (in category 'inline primitive generators generated code') -----
genLowcodeLoadArgumentUInt32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | value baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset value |
baseOffset := extA.
+ self allocateRegistersForLowcodeResultInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self loadNativeArgumentAddress: baseOffset to: TempReg.
self MoveM32: 0 r: TempReg R: value.
self ssPushNativeRegister: value.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentUInt64 (in category 'inline primitive generators generated code') -----
genLowcodeLoadArgumentUInt64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | valueHigh value valueLow baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset value valueLow valueHigh |
baseOffset := extA.
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeResultInteger2: [:valueLowValue :valueHighValue |
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ ].
- (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (valueLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
- (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
-
"TODO: Check the endianness"
self loadNativeArgumentAddress: baseOffset to: TempReg.
self MoveM32: 0 r: TempReg R: valueLow.
self MoveM32: 4 r: TempReg R: valueHigh.
self ssPushNativeRegister: valueLow secondRegister: valueHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeResultInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self loadNativeArgumentAddress: baseOffset to: TempReg.
self MoveM64: 0 r: TempReg R: value.
self ssPushNativeRegister: value.
].
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadArgumentUInt8 (in category 'inline primitive generators generated code') -----
genLowcodeLoadArgumentUInt8
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | value baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset value |
baseOffset := extA.
+ self allocateRegistersForLowcodeResultInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self loadNativeArgumentAddress: baseOffset to: TempReg.
self MoveM8: 0 r: TempReg R: value.
self ssPushNativeRegister: value.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadFloat32FromMemory (in category 'inline primitive generators generated code') -----
genLowcodeLoadFloat32FromMemory
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| pointer value |
+ self allocateRegistersForLowcodeIntegerResultFloat: [:pointerValue :valueValue |
+ pointer := pointerValue.
+ value := valueValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
- pointer = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
self MoveM32: 0 r: pointer Rs: value.
self ssPushNativeRegisterSingleFloat: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadFloat64FromMemory (in category 'inline primitive generators generated code') -----
genLowcodeLoadFloat64FromMemory
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| pointer value |
+ self allocateRegistersForLowcodeIntegerResultFloat: [:pointerValue :valueValue |
+ pointer := pointerValue.
+ value := valueValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
- pointer = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
self MoveM64: 0 r: pointer Rd: value.
self ssPushNativeRegisterDoubleFloat: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadInt16FromMemory (in category 'inline primitive generators generated code') -----
genLowcodeLoadInt16FromMemory
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| pointer value |
+ self allocateRegistersForLowcodeIntegerResultInteger: [:pointerValue :valueValue |
+ pointer := pointerValue.
+ value := valueValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
self MoveM16: 0 r: pointer R: value.
self SignExtend16R: value R: value.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadInt32FromMemory (in category 'inline primitive generators generated code') -----
genLowcodeLoadInt32FromMemory
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| pointer value |
+ self allocateRegistersForLowcodeIntegerResultInteger: [:pointerValue :valueValue |
+ pointer := pointerValue.
+ value := valueValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
self MoveM32: 0 r: pointer R: value.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadInt64FromMemory (in category 'inline primitive generators generated code') -----
genLowcodeLoadInt64FromMemory
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| valueHigh pointer value valueLow |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeIntegerResultInteger2: [:pointerValue :valueLowValue :valueHighValue |
+ pointer := pointerValue.
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (valueLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueLow := Arg1Reg)].
-
- (valueHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: pointer)) bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := SendNumArgsReg)].
- ((pointer = ReceiverResultReg or: [valueLow = ReceiverResultReg]) or: [valueHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
"TODO: Check the endianness"
self MoveM32: 0 r: pointer R: valueLow.
self MoveM32: 4 r: pointer R: valueHigh.
self ssPushNativeRegister: valueLow secondRegister: valueHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeIntegerResultInteger: [:pointerValue :valueValue |
+ pointer := pointerValue.
+ value := valueValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
self MoveM64: 0 r: pointer R: value.
self ssPushNativeRegister: value.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadInt8FromMemory (in category 'inline primitive generators generated code') -----
genLowcodeLoadInt8FromMemory
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| pointer value |
+ self allocateRegistersForLowcodeIntegerResultInteger: [:pointerValue :valueValue |
+ pointer := pointerValue.
+ value := valueValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
self MoveM8: 0 r: pointer R: value.
self SignExtend8R: value R: value.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalAddress (in category 'inline primitive generators generated code') -----
genLowcodeLoadLocalAddress
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | pointer baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset pointer |
baseOffset := extA.
+ self allocateRegistersForLowcodeResultInteger: [:pointerValue |
+ pointer := pointerValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- pointer = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self loadNativeLocalAddress: baseOffset to: pointer.
self ssPushNativeRegister: pointer.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalFloat32 (in category 'inline primitive generators generated code') -----
genLowcodeLoadLocalFloat32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | floatValue baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset floatValue |
baseOffset := extA.
+ self allocateRegistersForLowcodeResultFloat: [:floatValueValue |
+ floatValue := floatValueValue.
+ ].
- (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)].
self loadNativeLocalAddress: baseOffset to: TempReg.
self MoveM32: 0 r: TempReg Rs: floatValue.
self ssPushNativeRegisterSingleFloat: floatValue.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalFloat64 (in category 'inline primitive generators generated code') -----
genLowcodeLoadLocalFloat64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | doubleValue baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset doubleValue |
baseOffset := extA.
+ self allocateRegistersForLowcodeResultFloat: [:doubleValueValue |
+ doubleValue := doubleValueValue.
+ ].
- (doubleValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (doubleValue := DPFPReg0)].
self loadNativeLocalAddress: baseOffset to: TempReg.
self MoveM64: 0 r: TempReg Rd: doubleValue.
self ssPushNativeRegisterDoubleFloat: doubleValue.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalInt16 (in category 'inline primitive generators generated code') -----
genLowcodeLoadLocalInt16
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | value baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset value |
baseOffset := extA.
+ self allocateRegistersForLowcodeResultInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self loadNativeLocalAddress: baseOffset to: TempReg.
self MoveM16: 0 r: TempReg R: value.
self SignExtend16R: value R: value.
self ssPushNativeRegister: value.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalInt32 (in category 'inline primitive generators generated code') -----
genLowcodeLoadLocalInt32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | value baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset value |
baseOffset := extA.
+ self allocateRegistersForLowcodeResultInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self loadNativeLocalAddress: baseOffset to: TempReg.
self MoveM32: 0 r: TempReg R: value.
self ssPushNativeRegister: value.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalInt64 (in category 'inline primitive generators generated code') -----
genLowcodeLoadLocalInt64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | valueHigh value valueLow baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset value valueLow valueHigh |
baseOffset := extA.
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeResultInteger2: [:valueLowValue :valueHighValue |
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ ].
- (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (valueLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
- (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
-
"TODO: Check the endianness"
self loadNativeLocalAddress: baseOffset to: TempReg.
self MoveM32: 0 r: TempReg R: valueLow.
self MoveM32: 4 r: TempReg R: valueHigh.
self ssPushNativeRegister: valueLow secondRegister: valueHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeResultInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self loadNativeLocalAddress: baseOffset to: TempReg.
self MoveM64: 0 r: TempReg R: value.
self ssPushNativeRegister: value.
].
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalInt8 (in category 'inline primitive generators generated code') -----
genLowcodeLoadLocalInt8
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | value baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset value |
baseOffset := extA.
+ self allocateRegistersForLowcodeResultInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self loadNativeLocalAddress: baseOffset to: TempReg.
self MoveM8: 0 r: TempReg R: value.
self SignExtend8R: value R: value.
self ssPushNativeRegister: value.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalPointer (in category 'inline primitive generators generated code') -----
genLowcodeLoadLocalPointer
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | pointerResult baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset pointerResult |
baseOffset := extA.
+ self allocateRegistersForLowcodeResultInteger: [:pointerResultValue |
+ pointerResult := pointerResultValue.
+ ].
- (pointerResult := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointerResult := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- pointerResult = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self loadNativeLocalAddress: baseOffset to: TempReg.
self MoveMw: 0 r: TempReg R: pointerResult.
self ssPushNativeRegister: pointerResult.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalUInt16 (in category 'inline primitive generators generated code') -----
genLowcodeLoadLocalUInt16
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | value baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset value |
baseOffset := extA.
+ self allocateRegistersForLowcodeResultInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self loadNativeLocalAddress: baseOffset to: TempReg.
self MoveM16: 0 r: TempReg R: value.
self ssPushNativeRegister: value.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalUInt32 (in category 'inline primitive generators generated code') -----
genLowcodeLoadLocalUInt32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | value baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset value |
baseOffset := extA.
+ self allocateRegistersForLowcodeResultInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self loadNativeLocalAddress: baseOffset to: TempReg.
self MoveM32: 0 r: TempReg R: value.
self ssPushNativeRegister: value.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalUInt64 (in category 'inline primitive generators generated code') -----
genLowcodeLoadLocalUInt64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | valueHigh value valueLow baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset value valueLow valueHigh |
baseOffset := extA.
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeResultInteger2: [:valueLowValue :valueHighValue |
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ ].
- (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (valueLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
- (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
-
"TODO: Check the endianness"
self loadNativeLocalAddress: baseOffset to: TempReg.
self MoveM32: 0 r: TempReg R: valueLow.
self MoveM32: 4 r: TempReg R: valueHigh.
self ssPushNativeRegister: valueLow secondRegister: valueHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeResultInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self loadNativeLocalAddress: baseOffset to: TempReg.
self MoveM64: 0 r: TempReg R: value.
self ssPushNativeRegister: value.
].
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadLocalUInt8 (in category 'inline primitive generators generated code') -----
genLowcodeLoadLocalUInt8
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | value baseOffset |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | baseOffset value |
baseOffset := extA.
+ self allocateRegistersForLowcodeResultInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self loadNativeLocalAddress: baseOffset to: TempReg.
self MoveM8: 0 r: TempReg R: value.
self ssPushNativeRegister: value.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadObjectAt (in category 'inline primitive generators generated code') -----
genLowcodeLoadObjectAt
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| fieldIndex object |
+ self allocateRegistersForLowcodeIntegerOop: [:fieldIndexValue :objectValue |
+ fieldIndex := fieldIndexValue.
+ object := objectValue.
+ ].
- (fieldIndex := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (fieldIndex := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (object := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: fieldIndex))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (object := Arg1Reg)].
- (fieldIndex = ReceiverResultReg or: [object = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: fieldIndex.
self ssNativePop: 1.
self ssTop popToReg: object.
self ssPop: 1.
objectRepresentation genLcLoadObject: object at: fieldIndex.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadObjectField (in category 'inline primitive generators generated code') -----
genLowcodeLoadObjectField
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| fieldIndex object |
fieldIndex := extA.
+ self allocateRegistersForLowcodeOop: [:objectValue |
+ object := objectValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- object = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
objectRepresentation genLcLoadObject: object field: fieldIndex.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadPointerFromMemory (in category 'inline primitive generators generated code') -----
genLowcodeLoadPointerFromMemory
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| pointerResult pointer |
+ self allocateRegistersForLowcodeIntegerResultInteger: [:pointerValue :pointerResultValue |
+ pointer := pointerValue.
+ pointerResult := pointerResultValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (pointerResult := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (pointerResult := Arg1Reg)].
- (pointer = ReceiverResultReg or: [pointerResult = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
self MoveMw: 0 r: pointer R: pointerResult.
self ssPushNativeRegister: pointerResult.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadUInt16FromMemory (in category 'inline primitive generators generated code') -----
genLowcodeLoadUInt16FromMemory
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| pointer value |
+ self allocateRegistersForLowcodeIntegerResultInteger: [:pointerValue :valueValue |
+ pointer := pointerValue.
+ value := valueValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
self MoveM16: 0 r: pointer R: value.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadUInt32FromMemory (in category 'inline primitive generators generated code') -----
genLowcodeLoadUInt32FromMemory
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| pointer value |
+ self allocateRegistersForLowcodeIntegerResultInteger: [:pointerValue :valueValue |
+ pointer := pointerValue.
+ value := valueValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
self MoveM32: 0 r: pointer R: value.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadUInt64FromMemory (in category 'inline primitive generators generated code') -----
genLowcodeLoadUInt64FromMemory
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| valueHigh pointer value valueLow |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeIntegerResultInteger2: [:pointerValue :valueLowValue :valueHighValue |
+ pointer := pointerValue.
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (valueLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueLow := Arg1Reg)].
-
- (valueHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: pointer)) bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := SendNumArgsReg)].
- ((pointer = ReceiverResultReg or: [valueLow = ReceiverResultReg]) or: [valueHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
"TODO: Check the endianness"
self MoveM32: 0 r: pointer R: valueLow.
self MoveM32: 4 r: pointer R: valueHigh.
self ssPushNativeRegister: valueLow secondRegister: valueHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeIntegerResultInteger: [:pointerValue :valueValue |
+ pointer := pointerValue.
+ value := valueValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
self MoveM64: 0 r: pointer R: value.
self ssPushNativeRegister: value.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLoadUInt8FromMemory (in category 'inline primitive generators generated code') -----
genLowcodeLoadUInt8FromMemory
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| pointer value |
+ self allocateRegistersForLowcodeIntegerResultInteger: [:pointerValue :valueValue |
+ pointer := pointerValue.
+ value := valueValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
self MoveM8: 0 r: pointer R: value.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLocalFrameSize (in category 'inline primitive generators generated code') -----
genLowcodeLocalFrameSize
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | alignedSize size |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | size alignedSize |
size := extA.
self assert: needsFrame.
hasNativeFrame := true.
"Align the size to 16 bytes."
alignedSize := size + 15 bitAnd: -16.
"Mark the stack frame"
self annotate: (self MoveCw: (objectMemory splObj: LowcodeContextMark) R: TempReg) objRef: (objectMemory splObj: LowcodeContextMark).
self MoveR: TempReg Mw: self frameOffsetOfNativeFrameMark r: FPReg.
"Fetch the stack"
self MoveAw: coInterpreter nativeStackPointerAddress R: TempReg.
self AddCq: 1 R: TempReg.
self MoveR: TempReg Mw: self frameOffsetOfPreviousNativeStackPointer r: FPReg.
"Store the frame pointer"
self SubCq: alignedSize R: TempReg.
self MoveR: TempReg Mw: self frameOffsetOfNativeFramePointer r: FPReg.
"Store the new stack pointer"
self MoveR: TempReg Mw: self frameOffsetOfNativeStackPointer r: FPReg.
"Allocate space for the locals"
self SubCq: 1 + coInterpreter defaultNativeStackFrameSize R: TempReg.
self MoveR: TempReg Aw: coInterpreter nativeStackPointerAddress.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLockRegisters (in category 'inline primitive generators generated code') -----
genLowcodeLockRegisters
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self ssFlushAll.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeLockVM (in category 'inline primitive generators generated code') -----
genLowcodeLockVM
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeMalloc32 (in category 'inline primitive generators generated code') -----
genLowcodeMalloc32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| pointer size |
+ self allocateRegistersForLowcodeIntegerResultInteger: [:sizeValue :pointerValue |
+ size := sizeValue.
+ pointer := pointerValue.
+ ].
- (size := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (size := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (pointer := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: size))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (pointer := Arg1Reg)].
- (size = ReceiverResultReg or: [pointer = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: size.
self ssNativePop: 1.
self ssFlushAll.
size ~= ReceiverResultReg ifTrue: [self MoveR: size R: ReceiverResultReg ].
self CallRT: ceMallocTrampoline.
self MoveR: TempReg R: pointer.
self ssPushNativeRegister: pointer.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeMalloc64 (in category 'inline primitive generators generated code') -----
genLowcodeMalloc64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| sizeHigh size sizeLow pointer |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger2ResultInteger: [:sizeLowValue :sizeHighValue :pointerValue |
+ sizeLow := sizeLowValue.
+ sizeHigh := sizeHighValue.
+ pointer := pointerValue.
+ ].
- (sizeLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (sizeLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (sizeHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: sizeLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (sizeHigh := Arg1Reg)].
-
- (pointer := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: sizeLow)) bitOr: (self registerMaskFor: sizeHigh))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (pointer := SendNumArgsReg)].
- ((sizeLow = ReceiverResultReg or: [sizeHigh = ReceiverResultReg]) or: [pointer = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: sizeLow secondReg: sizeHigh.
self ssNativePop: 1.
self ssFlushAll.
sizeLow ~= ReceiverResultReg ifTrue: [self MoveR: sizeLow R: ReceiverResultReg ].
self CallRT: ceMallocTrampoline.
self MoveR: TempReg R: pointer.
self ssPushNativeRegister: pointer.
] ifFalse: [
+ self allocateRegistersForLowcodeIntegerResultInteger: [:sizeValue :pointerValue |
+ size := sizeValue.
+ pointer := pointerValue.
+ ].
- (size := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (size := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (pointer := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: size))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (pointer := Arg1Reg)].
- (size = ReceiverResultReg or: [pointer = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: size.
self ssNativePop: 1.
self ssFlushAll.
size ~= ReceiverResultReg ifTrue: [self MoveR: size R: ReceiverResultReg ].
self CallRT: ceMallocTrampoline.
self MoveR: TempReg R: pointer.
self ssPushNativeRegister: pointer.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeMemcpy32 (in category 'inline primitive generators generated code') -----
genLowcodeMemcpy32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | source size dest |
+ self allocateRegistersForLowcodeInteger3: [:sizeValue :sourceValue :destValue |
+ size := sizeValue.
+ source := sourceValue.
+ dest := destValue.
+ ].
- <option: #LowcodeVM> "Lowcode instruction generator"
- | source dest size |
- (size := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (size := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (source := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: size))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (source := Arg1Reg)].
-
- (dest := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: size)) bitOr: (self registerMaskFor: source))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (dest := SendNumArgsReg)].
- ((size = ReceiverResultReg or: [source = ReceiverResultReg]) or: [dest = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: size.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: source.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: dest.
self ssNativePop: 1.
self ssFlushAll.
backEnd genMemCopy: source to: dest size: size.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeMemcpy64 (in category 'inline primitive generators generated code') -----
genLowcodeMemcpy64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| source sizeLow sizeHigh dest size |
+ self allocateRegistersForLowcodeInteger3: [:sizeValue :sourceValue :destValue |
+ size := sizeValue.
+ source := sourceValue.
+ dest := destValue.
+ ].
- (size := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (size := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (source := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: size))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (source := Arg1Reg)].
-
- (dest := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: size)) bitOr: (self registerMaskFor: source))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (dest := SendNumArgsReg)].
- ((size = ReceiverResultReg or: [source = ReceiverResultReg]) or: [dest = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: size.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: source.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: dest.
self ssNativePop: 1.
self ssFlushAll.
backEnd genMemCopy: source to: dest size: sizeLow.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeMemcpyFixed (in category 'inline primitive generators generated code') -----
genLowcodeMemcpyFixed
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| source size dest |
size := extA.
+ self allocateRegistersForLowcodeInteger2: [:sourceValue :destValue |
+ source := sourceValue.
+ dest := destValue.
+ ].
- (source := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (source := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (dest := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: source))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (dest := Arg1Reg)].
- (source = ReceiverResultReg or: [dest = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: source.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: dest.
self ssNativePop: 1.
size = BytesPerWord ifTrue: [
self MoveMw: 0 r: source R: TempReg.
self MoveR: TempReg Mw: 0 r: dest.
] ifFalse: [
self ssFlushAll.
backEnd genMemCopy: source to: dest constantSize: size.
].
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeMoveFloat32ToPhysical (in category 'inline primitive generators generated code') -----
genLowcodeMoveFloat32ToPhysical
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self ssNativeTop nativeStackPopToReg: extA.
self ssNativePop: 1.
currentCallCleanUpSize := currentCallCleanUpSize + BytesPerWord.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeMoveFloat64ToPhysical (in category 'inline primitive generators generated code') -----
genLowcodeMoveFloat64ToPhysical
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self ssNativeTop nativeStackPopToReg: extA.
self ssNativePop: 1.
currentCallCleanUpSize := currentCallCleanUpSize + 8.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeMoveInt32ToPhysical (in category 'inline primitive generators generated code') -----
genLowcodeMoveInt32ToPhysical
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self ssNativeTop nativeStackPopToReg: extA.
self ssNativePop: 1.
currentCallCleanUpSize := currentCallCleanUpSize + BytesPerWord.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeMoveInt64ToPhysical (in category 'inline primitive generators generated code') -----
genLowcodeMoveInt64ToPhysical
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self ssNativeTop nativeStackPopToReg: extA.
self ssNativePop: 1.
currentCallCleanUpSize := currentCallCleanUpSize + 8.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeMovePointerToPhysical (in category 'inline primitive generators generated code') -----
genLowcodeMovePointerToPhysical
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self ssNativeTop nativeStackPopToReg: extA.
self ssNativePop: 1.
currentCallCleanUpSize := currentCallCleanUpSize + BytesPerWord.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeMul32 (in category 'inline primitive generators generated code') -----
genLowcodeMul32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second first |
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self MulR: second R: first.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeMul64 (in category 'inline primitive generators generated code') -----
genLowcodeMul64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | secondLow secondHigh firstHigh result resultLow resultHigh first second firstLow |
+ self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :resultValue |
+ second := secondValue.
+ first := firstValue.
+ result := resultValue.
+ ].
- <option: #LowcodeVM> "Lowcode instruction generator"
- | secondLow firstLow secondHigh result resultLow resultHigh first second firstHigh |
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
-
- (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (result := SendNumArgsReg)].
- ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeNeg32 (in category 'inline primitive generators generated code') -----
genLowcodeNeg32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value |
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self NegateR: value.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeNeg64 (in category 'inline primitive generators generated code') -----
genLowcodeNeg64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| valueHigh value valueLow |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger2: [:valueLowValue :valueHighValue |
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ ].
- (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (valueLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
- (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
self ssNativePop: 1.
"Two complement negation"
self NotR: valueLow.
self NotR: valueHigh.
self AddCq: 1 R: valueLow.
self AddcCq: 0 R: valueHigh.
self ssPushNativeRegister: valueLow secondRegister: valueHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self NegateR: value.
self ssPushNativeRegister: value.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeNot32 (in category 'inline primitive generators generated code') -----
genLowcodeNot32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value |
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self NotR: value.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeNot64 (in category 'inline primitive generators generated code') -----
genLowcodeNot64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| valueHigh value valueLow |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger2: [:valueLowValue :valueHighValue |
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ ].
- (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (valueLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
- (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
self ssNativePop: 1.
self NotR: valueLow.
self NotR: valueHigh.
self ssPushNativeRegister: valueLow secondRegister: valueHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self NotR: value.
self ssPushNativeRegister: value.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeOopEqual (in category 'inline primitive generators generated code') -----
genLowcodeOopEqual
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value contJump falseJump first second |
+ self allocateRegistersForLowcodeOop2ResultInteger: [:secondValue :firstValue :valueValue |
+ second := secondValue.
+ first := firstValue.
+ value := valueValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
-
- (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := SendNumArgsReg)].
- ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: second.
self ssPop: 1.
self ssTop popToReg: first.
self ssPop: 1.
self CmpR: second R: first.
falseJump := self JumpNonZero: 0.
"True result"
self MoveCq: 1 R: first.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: first.
contJump jmpTarget: self Label.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeOopNotEqual (in category 'inline primitive generators generated code') -----
genLowcodeOopNotEqual
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second falseJump contJump first |
+ self allocateRegistersForLowcodeOop2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: second.
self ssPop: 1.
self ssTop popToReg: first.
self ssPop: 1.
self CmpR: second R: first.
falseJump := self JumpZero: 0.
"True result"
self MoveCq: 1 R: first.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: first.
contJump jmpTarget: self Label.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeOopSmallIntegerToInt32 (in category 'inline primitive generators generated code') -----
genLowcodeOopSmallIntegerToInt32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| object |
+ self allocateRegistersForLowcodeOop: [:objectValue |
+ object := objectValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- object = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
objectRepresentation genConvertSmallIntegerToIntegerInReg: object.
self ssPushNativeRegister: object.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeOopSmallIntegerToInt64 (in category 'inline primitive generators generated code') -----
genLowcodeOopSmallIntegerToInt64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| valueHigh object value valueLow |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeOopResultInteger2: [:objectValue :valueLowValue :valueHighValue |
+ object := objectValue.
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (valueLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueLow := Arg1Reg)].
-
- (valueHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: object)) bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := SendNumArgsReg)].
- ((object = ReceiverResultReg or: [valueLow = ReceiverResultReg]) or: [valueHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
objectRepresentation genConvertSmallIntegerToIntegerInReg: object.
self MoveCq: 0 R: valueHigh.
self ssPushNativeRegister: object secondRegister: valueHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue |
+ object := objectValue.
+ value := valueValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
objectRepresentation genConvertSmallIntegerToIntegerInReg: object.
self ssPushNativeRegister: object.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeOopToBoolean32 (in category 'inline primitive generators generated code') -----
genLowcodeOopToBoolean32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| object |
+ self allocateRegistersForLowcodeOop: [:objectValue |
+ object := objectValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- object = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
self annotate: (self SubCw: objectMemory falseObject R: object) objRef: objectMemory falseObject.
self ssPushNativeRegister: object.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeOopToBoolean64 (in category 'inline primitive generators generated code') -----
genLowcodeOopToBoolean64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| valueHigh object value valueLow |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeOopResultInteger2: [:objectValue :valueLowValue :valueHighValue |
+ object := objectValue.
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (valueLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueLow := Arg1Reg)].
-
- (valueHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: object)) bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := SendNumArgsReg)].
- ((object = ReceiverResultReg or: [valueLow = ReceiverResultReg]) or: [valueHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
self MoveCq: 0 R: valueHigh.
self annotate: (self SubCw: objectMemory falseObject R: object) objRef: objectMemory falseObject.
self ssPushNativeRegister: object secondRegister: valueHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue |
+ object := objectValue.
+ value := valueValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
self annotate: (self SubCw: objectMemory falseObject R: object) objRef: objectMemory falseObject.
self ssPushNativeRegister: object.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeOopToFloat32 (in category 'inline primitive generators generated code') -----
genLowcodeOopToFloat32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| object value |
+ self allocateRegistersForLowcodeOopResultFloat: [:objectValue :valueValue |
+ object := objectValue.
+ value := valueValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
- object = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
self ssFlushAll.
objectRepresentation genLcOop: object toFloat32: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeOopToFloat64 (in category 'inline primitive generators generated code') -----
genLowcodeOopToFloat64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| object value |
+ self allocateRegistersForLowcodeOopResultFloat: [:objectValue :valueValue |
+ object := objectValue.
+ value := valueValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
- object = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
self ssFlushAll.
objectRepresentation genLcOop: object toFloat64: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeOopToInt32 (in category 'inline primitive generators generated code') -----
genLowcodeOopToInt32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| object |
+ self allocateRegistersForLowcodeOop: [:objectValue |
+ object := objectValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- object = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
self ssFlushAll.
objectRepresentation genLcOopToInt32: object.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeOopToInt64 (in category 'inline primitive generators generated code') -----
genLowcodeOopToInt64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| valueHigh object value valueLow |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeOopResultInteger2: [:objectValue :valueLowValue :valueHighValue |
+ object := objectValue.
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (valueLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueLow := Arg1Reg)].
-
- (valueHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: object)) bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := SendNumArgsReg)].
- ((object = ReceiverResultReg or: [valueLow = ReceiverResultReg]) or: [valueHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
self ssFlushAll.
objectRepresentation genLcOop: object toInt64: valueLow highPart: valueHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue |
+ object := objectValue.
+ value := valueValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
self ssFlushAll.
objectRepresentation genLcOopToInt64: object.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeOopToPointer (in category 'inline primitive generators generated code') -----
genLowcodeOopToPointer
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| object |
+ self allocateRegistersForLowcodeOop: [:objectValue |
+ object := objectValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- object = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
objectRepresentation genLcOopToPointer: object.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeOopToPointerReinterpret (in category 'inline primitive generators generated code') -----
genLowcodeOopToPointerReinterpret
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| object pointer |
+ self allocateRegistersForLowcodeOopResultInteger: [:objectValue :pointerValue |
+ object := objectValue.
+ pointer := pointerValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (pointer := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (pointer := Arg1Reg)].
- (object = ReceiverResultReg or: [pointer = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
"TODO: Generate a nop here"
self ssPushNativeRegister: object.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeOopToUInt32 (in category 'inline primitive generators generated code') -----
genLowcodeOopToUInt32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| object value |
+ self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue |
+ object := objectValue.
+ value := valueValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
self ssFlushAll.
objectRepresentation genLcOopToUInt32: object.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeOopToUInt64 (in category 'inline primitive generators generated code') -----
genLowcodeOopToUInt64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| valueHigh object value valueLow |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeOopResultInteger2: [:objectValue :valueLowValue :valueHighValue |
+ object := objectValue.
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (valueLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueLow := Arg1Reg)].
-
- (valueHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: object)) bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := SendNumArgsReg)].
- ((object = ReceiverResultReg or: [valueLow = ReceiverResultReg]) or: [valueHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
self ssFlushAll.
objectRepresentation genLcOop: object toUInt64: valueLow highPart: valueHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeOopResultInteger: [:objectValue :valueValue |
+ object := objectValue.
+ value := valueValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: object))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (object = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
self ssFlushAll.
objectRepresentation genLcOopToUInt64: object.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeOr32 (in category 'inline primitive generators generated code') -----
genLowcodeOr32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second result first |
+ self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :resultValue |
+ second := secondValue.
+ first := firstValue.
+ result := resultValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
-
- (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (result := SendNumArgsReg)].
- ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self OrR: second R: first.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeOr64 (in category 'inline primitive generators generated code') -----
genLowcodeOr64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | secondLow secondHigh firstHigh first second firstLow |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | secondLow firstLow secondHigh first second firstHigh |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger4: [:secondLowValue :secondHighValue :firstLowValue :firstHighValue |
+ secondLow := secondLowValue.
+ secondHigh := secondHighValue.
+ firstLow := firstLowValue.
+ firstHigh := firstHighValue.
+ ].
- (secondLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (secondLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (secondHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: secondLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (secondHigh := Arg1Reg)].
-
- (firstLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (firstLow := SendNumArgsReg)].
-
- (firstHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh)) bitOr: (self registerMaskFor: firstLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (firstHigh := ClassReg)].
- (((secondLow = ReceiverResultReg or: [secondHigh = ReceiverResultReg]) or: [firstLow = ReceiverResultReg]) or: [firstHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: secondLow secondReg: secondHigh.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: firstLow secondReg: firstHigh.
self ssNativePop: 1.
self OrR: secondLow R: firstLow.
self OrR: secondHigh R: firstHigh.
self ssPushNativeRegister: firstLow secondRegister: firstHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self OrR: second R: first.
self ssPushNativeRegister: first.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePerformCallout (in category 'inline primitive generators generated code') -----
genLowcodePerformCallout
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self callSwitchToCStack.
self MoveCw: extA R: TempReg.
self CallRT: ceFFICalloutTrampoline.
self annotateBytecode: self Label.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePerformCalloutIndirect (in category 'inline primitive generators generated code') -----
genLowcodePerformCalloutIndirect
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self ssNativeTop nativeStackPopToReg: TempReg.
self ssNativePop: 1.
self callSwitchToCStack.
self CallRT: ceFFICalloutTrampoline.
self annotateBytecode: self Label.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePin (in category 'inline primitive generators generated code') -----
genLowcodePin
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| object |
+ self allocateRegistersForLowcodeOop: [:objectValue |
+ object := objectValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- object = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePlaftormCode (in category 'inline primitive generators generated code') -----
genLowcodePlaftormCode
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePointerAddConstantOffset (in category 'inline primitive generators generated code') -----
genLowcodePointerAddConstantOffset
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| base offset |
offset := extB.
+ self allocateRegistersForLowcodeInteger: [:baseValue |
+ base := baseValue.
+ ].
- (base := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (base := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- base = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: base.
self ssNativePop: 1.
self AddCq: offset R: base.
self ssPushNativeRegister: base.
extB := 0.
numExtB := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePointerAddOffset32 (in category 'inline primitive generators generated code') -----
genLowcodePointerAddOffset32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| base offset |
+ self allocateRegistersForLowcodeInteger2: [:offsetValue :baseValue |
+ offset := offsetValue.
+ base := baseValue.
+ ].
- (offset := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (offset := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (base := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: offset))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (base := Arg1Reg)].
- (offset = ReceiverResultReg or: [base = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: offset.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: base.
self ssNativePop: 1.
self AddR: offset R: base.
self ssPushNativeRegister: base.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePointerAddOffset64 (in category 'inline primitive generators generated code') -----
genLowcodePointerAddOffset64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| offsetHigh base offset offsetLow |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger3: [:offsetLowValue :offsetHighValue :baseValue |
+ offsetLow := offsetLowValue.
+ offsetHigh := offsetHighValue.
+ base := baseValue.
+ ].
- (offsetLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (offsetLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (offsetHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: offsetLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (offsetHigh := Arg1Reg)].
-
- (base := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: offsetLow)) bitOr: (self registerMaskFor: offsetHigh))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (base := SendNumArgsReg)].
- ((offsetLow = ReceiverResultReg or: [offsetHigh = ReceiverResultReg]) or: [base = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: offsetLow secondReg: offsetHigh.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: base.
self ssNativePop: 1.
self AddR: offsetLow R: base.
self ssPushNativeRegister: base.
] ifFalse: [
+ self allocateRegistersForLowcodeInteger2: [:offsetValue :baseValue |
+ offset := offsetValue.
+ base := baseValue.
+ ].
- (offset := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (offset := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (base := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: offset))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (base := Arg1Reg)].
- (offset = ReceiverResultReg or: [base = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: offset.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: base.
self ssNativePop: 1.
self AddR: offset R: base.
self ssPushNativeRegister: base.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePointerEqual (in category 'inline primitive generators generated code') -----
genLowcodePointerEqual
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second falseJump contJump first |
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpR: second R: first.
falseJump := self JumpNonZero: 0.
"True result"
self MoveCq: 1 R: first.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: first.
contJump jmpTarget: self Label.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePointerNotEqual (in category 'inline primitive generators generated code') -----
genLowcodePointerNotEqual
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second falseJump contJump first |
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpR: second R: first.
falseJump := self JumpZero: 0.
"True result"
self MoveCq: 1 R: first.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: first.
contJump jmpTarget: self Label.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePointerToInt32 (in category 'inline primitive generators generated code') -----
genLowcodePointerToInt32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| pointer |
+ self allocateRegistersForLowcodeInteger: [:pointerValue |
+ pointer := pointerValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- pointer = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
"TODO: Perform a NOP here"
self ssPushNativeRegister: pointer.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePointerToInt64 (in category 'inline primitive generators generated code') -----
genLowcodePointerToInt64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| resultLow pointer result resultHigh |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeIntegerResultInteger2: [:pointerValue :resultLowValue :resultHighValue |
+ pointer := pointerValue.
+ resultLow := resultLowValue.
+ resultHigh := resultHighValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (resultLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (resultLow := Arg1Reg)].
-
- (resultHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: pointer)) bitOr: (self registerMaskFor: resultLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (resultHigh := SendNumArgsReg)].
- ((pointer = ReceiverResultReg or: [resultLow = ReceiverResultReg]) or: [resultHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
self MoveR: pointer R: resultLow.
self MoveCq: 0 R: resultHigh.
self ssPushNativeRegister: resultLow secondRegister: resultHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeIntegerResultInteger: [:pointerValue :resultValue |
+ pointer := pointerValue.
+ result := resultValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (result := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (result := Arg1Reg)].
- (pointer = ReceiverResultReg or: [result = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
self ssPushNativeRegister: pointer.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePointerToOop (in category 'inline primitive generators generated code') -----
genLowcodePointerToOop
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| pointer pointerClassLiteral |
pointerClassLiteral := self getLiteral: extA.
+ self allocateRegistersForLowcodeInteger: [:pointerValue |
+ pointer := pointerValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- pointer = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
self ssFlushAll.
objectRepresentation genLcPointerToOop: pointer class: pointerClassLiteral.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePointerToOopReinterprer (in category 'inline primitive generators generated code') -----
genLowcodePointerToOopReinterprer
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| pointer |
+ self allocateRegistersForLowcodeInteger: [:pointerValue |
+ pointer := pointerValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- pointer = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
"TODO: Generate a nop here"
self ssPushRegister: pointer.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePopFloat32 (in category 'inline primitive generators generated code') -----
genLowcodePopFloat32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value |
+ self allocateRegistersForLowcodeFloat: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePopFloat64 (in category 'inline primitive generators generated code') -----
genLowcodePopFloat64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value |
+ self allocateRegistersForLowcodeFloat: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePopInt32 (in category 'inline primitive generators generated code') -----
genLowcodePopInt32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value |
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePopInt64 (in category 'inline primitive generators generated code') -----
genLowcodePopInt64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| valueHigh value valueLow |
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePopMultipleNative (in category 'inline primitive generators generated code') -----
genLowcodePopMultipleNative
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self ssPopNativeSize: extA.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePopPointer (in category 'inline primitive generators generated code') -----
genLowcodePopPointer
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| pointerValue |
+ self allocateRegistersForLowcodeInteger: [:pointerValueValue |
+ pointerValue := pointerValueValue.
+ ].
- (pointerValue := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointerValue := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- pointerValue = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointerValue.
self ssNativePop: 1.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePushCalloutResultFloat32 (in category 'inline primitive generators generated code') -----
genLowcodePushCalloutResultFloat32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
backEnd cFloatResultToRs: DPFPReg0.
self ssPushNativeRegisterSingleFloat: DPFPReg0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePushCalloutResultFloat64 (in category 'inline primitive generators generated code') -----
genLowcodePushCalloutResultFloat64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
backEnd cFloatResultToRd: DPFPReg0.
self ssPushNativeRegisterDoubleFloat: DPFPReg0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePushCalloutResultInt32 (in category 'inline primitive generators generated code') -----
genLowcodePushCalloutResultInt32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self MoveR: backEnd cResultRegister R: ReceiverResultReg.
self ssPushNativeRegister: ReceiverResultReg.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePushCalloutResultInt64 (in category 'inline primitive generators generated code') -----
genLowcodePushCalloutResultInt64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
BytesPerWord = 4 ifTrue: [
self MoveR: backEnd cResultRegisterLow R: ReceiverResultReg.
self MoveR: backEnd cResultRegisterHigh R: Arg0Reg.
self ssPushNativeRegister: ReceiverResultReg secondRegister: Arg0Reg.
] ifFalse: [
self MoveR: backEnd cResultRegister R: ReceiverResultReg.
self ssPushNativeRegister: ReceiverResultReg.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePushCalloutResultPointer (in category 'inline primitive generators generated code') -----
genLowcodePushCalloutResultPointer
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self MoveR: backEnd cResultRegister R: ReceiverResultReg.
self ssPushNativeRegister: ReceiverResultReg.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePushConstantUInt32 (in category 'inline primitive generators generated code') -----
genLowcodePushConstantUInt32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| constant |
constant := extA.
self ssPushNativeConstantInt32: constant.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePushConstantUInt64 (in category 'inline primitive generators generated code') -----
genLowcodePushConstantUInt64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| constant |
constant := extA.
self ssPushNativeConstantInt64: constant.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePushNullPointer (in category 'inline primitive generators generated code') -----
genLowcodePushNullPointer
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self ssPushNativeConstantPointer: 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePushOne32 (in category 'inline primitive generators generated code') -----
genLowcodePushOne32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self ssPushNativeConstantInt32: 1.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePushOne64 (in category 'inline primitive generators generated code') -----
genLowcodePushOne64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self ssPushNativeConstantInt64: 1.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePushOneFloat32 (in category 'inline primitive generators generated code') -----
genLowcodePushOneFloat32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self ssPushNativeConstantFloat32: 1.0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePushOneFloat64 (in category 'inline primitive generators generated code') -----
genLowcodePushOneFloat64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self ssPushNativeConstantFloat64: 1.0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePushPhysicalFloat32 (in category 'inline primitive generators generated code') -----
genLowcodePushPhysicalFloat32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| registerID |
registerID := extA.
self abort.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePushPhysicalFloat64 (in category 'inline primitive generators generated code') -----
genLowcodePushPhysicalFloat64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| registerID |
registerID := extA.
self abort.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePushPhysicalInt32 (in category 'inline primitive generators generated code') -----
genLowcodePushPhysicalInt32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| registerID |
registerID := extA.
self abort.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePushPhysicalInt64 (in category 'inline primitive generators generated code') -----
genLowcodePushPhysicalInt64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| registerID |
registerID := extA.
self abort.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePushPhysicalPointer (in category 'inline primitive generators generated code') -----
genLowcodePushPhysicalPointer
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| registerID |
registerID := extA.
self abort.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePushSessionIdentifier (in category 'inline primitive generators generated code') -----
genLowcodePushSessionIdentifier
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self ssPushNativeConstantInt32: coInterpreter getThisSessionID.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePushZero32 (in category 'inline primitive generators generated code') -----
genLowcodePushZero32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self ssPushNativeConstantInt32: 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePushZero64 (in category 'inline primitive generators generated code') -----
genLowcodePushZero64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self ssPushNativeConstantInt64: 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePushZeroFloat32 (in category 'inline primitive generators generated code') -----
genLowcodePushZeroFloat32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self ssPushNativeConstantFloat32: 0.0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodePushZeroFloat64 (in category 'inline primitive generators generated code') -----
genLowcodePushZeroFloat64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self ssPushNativeConstantFloat64: 0.0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeRem32 (in category 'inline primitive generators generated code') -----
genLowcodeRem32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second first |
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self DivR: second R: first Quo: second Rem: first.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeRem64 (in category 'inline primitive generators generated code') -----
genLowcodeRem64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | secondLow secondHigh firstHigh result resultLow resultHigh first second firstLow |
+ self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :resultValue |
+ second := secondValue.
+ first := firstValue.
+ result := resultValue.
+ ].
- <option: #LowcodeVM> "Lowcode instruction generator"
- | secondLow firstLow secondHigh result resultLow resultHigh first second firstHigh |
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
-
- (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (result := SendNumArgsReg)].
- ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeRightShift32 (in category 'inline primitive generators generated code') -----
genLowcodeRightShift32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value shiftAmount |
+ self allocateRegistersForLowcodeInteger2: [:shiftAmountValue :valueValue |
+ shiftAmount := shiftAmountValue.
+ value := valueValue.
+ ].
- (shiftAmount := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (shiftAmount := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: shiftAmount))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (shiftAmount = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: shiftAmount.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self LogicalShiftRightR: shiftAmount R: value.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeRightShift64 (in category 'inline primitive generators generated code') -----
genLowcodeRightShift64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | value result shiftAmountHigh shiftAmount resultLow valueLow resultHigh shiftAmountLow valueHigh |
+ self allocateRegistersForLowcodeInteger2ResultInteger: [:shiftAmountValue :valueValue :resultValue |
+ shiftAmount := shiftAmountValue.
+ value := valueValue.
+ result := resultValue.
+ ].
- <option: #LowcodeVM> "Lowcode instruction generator"
- | value result shiftAmount shiftAmountHigh resultLow valueLow resultHigh shiftAmountLow valueHigh |
- (shiftAmount := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (shiftAmount := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: shiftAmount))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
-
- (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: shiftAmount)) bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (result := SendNumArgsReg)].
- ((shiftAmount = ReceiverResultReg or: [value = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: shiftAmount.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeSignExtend32From16 (in category 'inline primitive generators generated code') -----
genLowcodeSignExtend32From16
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value |
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self SignExtend16R: value R: value.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeSignExtend32From8 (in category 'inline primitive generators generated code') -----
genLowcodeSignExtend32From8
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value |
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self SignExtend8R: value R: value.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeSignExtend64From16 (in category 'inline primitive generators generated code') -----
genLowcodeSignExtend64From16
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value isNegative cont valueLow valueHigh |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger2: [:valueLowValue :valueHighValue |
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ ].
- (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (valueLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
- (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
self ssNativePop: 1.
self SignExtend16R: valueLow R: valueLow.
"Check the sign to set the high word"
self CmpCq: 0 R: valueLow.
"Positive"
isNegative := self JumpLess: 0.
self MoveCq: 0 R: valueHigh.
cont := self Jump: 0.
"Negative"
isNegative jmpTarget: (self MoveCq: -1 R: valueHigh).
cont jmpTarget: self Label.
self ssPushNativeRegister: valueLow secondRegister: valueHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self SignExtend16R: value R: value.
self ssPushNativeRegister: value.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeSignExtend64From32 (in category 'inline primitive generators generated code') -----
genLowcodeSignExtend64From32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value result resultLow resultHigh isNegative cont |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeIntegerResultInteger2: [:valueValue :resultLowValue :resultHighValue |
+ value := valueValue.
+ resultLow := resultLowValue.
+ resultHigh := resultHighValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (resultLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (resultLow := Arg1Reg)].
-
- (resultHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: value)) bitOr: (self registerMaskFor: resultLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (resultHigh := SendNumArgsReg)].
- ((value = ReceiverResultReg or: [resultLow = ReceiverResultReg]) or: [resultHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self MoveR: value R: resultLow.
"Check the sign to set the high word"
self CmpCq: 0 R: value.
"Positive"
isNegative := self JumpLess: 0.
self MoveCq: 0 R: resultHigh.
cont := self Jump: 0.
"Negative"
isNegative jmpTarget: (self MoveCq: -1 R: resultHigh).
cont jmpTarget: self Label.
self ssPushNativeRegister: resultLow secondRegister: resultHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeIntegerResultInteger: [:valueValue :resultValue |
+ value := valueValue.
+ result := resultValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (result := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (result := Arg1Reg)].
- (value = ReceiverResultReg or: [result = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self SignExtend32R: value R: value.
self ssPushNativeRegister: value.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeSignExtend64From8 (in category 'inline primitive generators generated code') -----
genLowcodeSignExtend64From8
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value result resultLow resultHigh isNegative valueLow cont valueHigh |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger2ResultInteger2: [:valueLowValue :valueHighValue :resultLowValue :resultHighValue |
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ resultLow := resultLowValue.
+ resultHigh := resultHighValue.
+ ].
- (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (valueLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
-
- (resultLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: valueLow)) bitOr: (self registerMaskFor: valueHigh))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (resultLow := SendNumArgsReg)].
-
- (resultHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: valueLow)) bitOr: (self registerMaskFor: valueHigh)) bitOr: (self registerMaskFor: resultLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (resultHigh := ClassReg)].
- (((valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) or: [resultLow = ReceiverResultReg]) or: [resultHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
self ssNativePop: 1.
self SignExtend8R: valueLow R: valueLow.
"Check the sign to set the high word"
self CmpCq: 0 R: valueLow.
"Positive"
isNegative := self JumpLess: 0.
self MoveCq: 0 R: valueHigh.
cont := self Jump: 0.
"Negative"
isNegative jmpTarget: (self MoveCq: -1 R: valueHigh).
cont jmpTarget: self Label.
self ssPushNativeRegister: valueLow secondRegister: valueHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeIntegerResultInteger: [:valueValue :resultValue |
+ value := valueValue.
+ result := resultValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (result := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (result := Arg1Reg)].
- (value = ReceiverResultReg or: [result = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self ZeroExtend16R: value R: value.
self ssPushNativeRegister: value.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeSmallInt32ToOop (in category 'inline primitive generators generated code') -----
genLowcodeSmallInt32ToOop
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value |
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
objectRepresentation genConvertIntegerToSmallIntegerInReg: value.
self ssPushRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeStoreFloat32ToMemory (in category 'inline primitive generators generated code') -----
genLowcodeStoreFloat32ToMemory
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| floatValue pointer |
+ self allocateRegistersForLowcodeFloatInteger: [:floatValueValue :pointerValue |
+ floatValue := floatValueValue.
+ pointer := pointerValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (floatValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (floatValue := DPFPReg0)].
- pointer = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: floatValue.
self ssNativePop: 1.
self MoveRs: floatValue M32: 0 r: pointer.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeStoreFloat64ToMemory (in category 'inline primitive generators generated code') -----
genLowcodeStoreFloat64ToMemory
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| doubleValue pointer |
+ self allocateRegistersForLowcodeFloatInteger: [:doubleValueValue :pointerValue |
+ doubleValue := doubleValueValue.
+ pointer := pointerValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (doubleValue := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (doubleValue := DPFPReg0)].
- pointer = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: doubleValue.
self ssNativePop: 1.
self MoveRd: doubleValue M64: 0 r: pointer.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeStoreInt16ToMemory (in category 'inline primitive generators generated code') -----
genLowcodeStoreInt16ToMemory
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| pointer value |
+ self allocateRegistersForLowcodeInteger2: [:pointerValue :valueValue |
+ pointer := pointerValue.
+ value := valueValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self MoveR: value R: TempReg.
self MoveR: TempReg M16: 0 r: pointer.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeStoreInt32ToMemory (in category 'inline primitive generators generated code') -----
genLowcodeStoreInt32ToMemory
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| pointer value |
+ self allocateRegistersForLowcodeInteger2: [:pointerValue :valueValue |
+ pointer := pointerValue.
+ value := valueValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self MoveR: value M32: 0 r: pointer.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeStoreInt64ToMemory (in category 'inline primitive generators generated code') -----
genLowcodeStoreInt64ToMemory
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| valueHigh pointer value valueLow |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger3: [:pointerValue :valueLowValue :valueHighValue |
+ pointer := pointerValue.
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (valueLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueLow := Arg1Reg)].
-
- (valueHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: pointer)) bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := SendNumArgsReg)].
- ((pointer = ReceiverResultReg or: [valueLow = ReceiverResultReg]) or: [valueHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
self ssNativePop: 1.
self MoveR: valueLow M32: 0 r: pointer.
self MoveR: valueHigh M32: 4 r: pointer.
] ifFalse: [
+ self allocateRegistersForLowcodeInteger2: [:pointerValue :valueValue |
+ pointer := pointerValue.
+ value := valueValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self MoveR: value M64: 0 r: pointer.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeStoreInt8ToMemory (in category 'inline primitive generators generated code') -----
genLowcodeStoreInt8ToMemory
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| pointer value |
+ self allocateRegistersForLowcodeInteger2: [:pointerValue :valueValue |
+ pointer := pointerValue.
+ value := valueValue.
+ ].
- (pointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (value := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: pointer))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := Arg1Reg)].
- (pointer = ReceiverResultReg or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointer.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self MoveR: value R: TempReg.
self MoveR: TempReg M8: 0 r: pointer.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeStoreLocalFloat32 (in category 'inline primitive generators generated code') -----
genLowcodeStoreLocalFloat32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value baseOffset |
baseOffset := extA.
+ self allocateRegistersForLowcodeFloat: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self loadNativeLocalAddress: baseOffset to: TempReg.
self MoveRs: value M32: 0 r: TempReg.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeStoreLocalFloat64 (in category 'inline primitive generators generated code') -----
genLowcodeStoreLocalFloat64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value baseOffset |
baseOffset := extA.
+ self allocateRegistersForLowcodeFloat: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (value := DPFPReg0)].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self loadNativeLocalAddress: baseOffset to: TempReg.
self MoveRd: value M64: 0 r: TempReg.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeStoreLocalInt16 (in category 'inline primitive generators generated code') -----
genLowcodeStoreLocalInt16
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value baseOffset |
baseOffset := extA.
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self MoveR: value R: TempReg.
self loadNativeLocalAddress: baseOffset to: value.
self MoveR: TempReg M16: 0 r: value.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeStoreLocalInt32 (in category 'inline primitive generators generated code') -----
genLowcodeStoreLocalInt32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value baseOffset |
baseOffset := extA.
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self loadNativeLocalAddress: baseOffset to: TempReg.
self MoveR: value M32: 0 r: TempReg.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeStoreLocalInt64 (in category 'inline primitive generators generated code') -----
genLowcodeStoreLocalInt64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| valueHigh value valueLow baseOffset |
baseOffset := extA.
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger2: [:valueLowValue :valueHighValue |
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ ].
- (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (valueLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
- (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
self ssNativePop: 1.
self loadNativeLocalAddress: baseOffset to: TempReg.
self MoveR: valueLow M32: 0 r: TempReg.
self MoveR: valueHigh M32: 4 r: TempReg.
] ifFalse: [
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self MoveR: value M64: 0 r: TempReg.
].
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeStoreLocalInt8 (in category 'inline primitive generators generated code') -----
genLowcodeStoreLocalInt8
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value baseOffset |
baseOffset := extA.
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self MoveR: value R: TempReg.
self loadNativeLocalAddress: baseOffset to: value.
self MoveR: TempReg M8: 0 r: value.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeStoreLocalPointer (in category 'inline primitive generators generated code') -----
genLowcodeStoreLocalPointer
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| pointerValue baseOffset |
baseOffset := extA.
+ self allocateRegistersForLowcodeInteger: [:pointerValueValue |
+ pointerValue := pointerValueValue.
+ ].
- (pointerValue := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (pointerValue := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- pointerValue = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: pointerValue.
self ssNativePop: 1.
self loadNativeLocalAddress: baseOffset to: TempReg.
self MoveR: pointerValue Mw: 0 r: TempReg.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeStoreObjectField (in category 'inline primitive generators generated code') -----
genLowcodeStoreObjectField
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| fieldIndex object value |
fieldIndex := extA.
+ self allocateRegistersForLowcodeOop2: [:valueValue :objectValue |
+ value := valueValue.
+ object := objectValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (object := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (object := Arg1Reg)].
- (value = ReceiverResultReg or: [object = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: value.
self ssPop: 1.
self ssTop popToReg: object.
self ssPop: 1.
objectRepresentation genLcStore: value object: object field: fieldIndex.
extA := 0.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeStoreObjectFieldAt (in category 'inline primitive generators generated code') -----
genLowcodeStoreObjectFieldAt
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| fieldIndex object value |
+ self allocateRegistersForLowcodeIntegerOop2: [:fieldIndexValue :valueValue :objectValue |
+ fieldIndex := fieldIndexValue.
+ value := valueValue.
+ object := objectValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (fieldIndex := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (fieldIndex := Arg1Reg)].
-
- (object := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: value)) bitOr: (self registerMaskFor: fieldIndex))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (object := SendNumArgsReg)].
- ((value = ReceiverResultReg or: [fieldIndex = ReceiverResultReg]) or: [object = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: value.
self ssPop: 1.
self ssNativeTop nativePopToReg: fieldIndex.
self ssNativePop: 1.
self ssTop popToReg: object.
self ssPop: 1.
objectRepresentation genLcStore: value object: object at: fieldIndex.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeStorePointerToMemory (in category 'inline primitive generators generated code') -----
genLowcodeStorePointerToMemory
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| memoryPointer pointerValue |
+ self allocateRegistersForLowcodeInteger2: [:memoryPointerValue :pointerValueValue |
+ memoryPointer := memoryPointerValue.
+ pointerValue := pointerValueValue.
+ ].
- (memoryPointer := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (memoryPointer := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (pointerValue := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: memoryPointer))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (pointerValue := Arg1Reg)].
- (memoryPointer = ReceiverResultReg or: [pointerValue = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: memoryPointer.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: pointerValue.
self ssNativePop: 1.
self MoveR: pointerValue Mw: 0 r: memoryPointer.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeSub32 (in category 'inline primitive generators generated code') -----
genLowcodeSub32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second first |
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self SubR: second R: first.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeSub64 (in category 'inline primitive generators generated code') -----
genLowcodeSub64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | secondLow secondHigh firstHigh first second firstLow |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | secondLow firstLow secondHigh first second firstHigh |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger4: [:secondLowValue :secondHighValue :firstLowValue :firstHighValue |
+ secondLow := secondLowValue.
+ secondHigh := secondHighValue.
+ firstLow := firstLowValue.
+ firstHigh := firstHighValue.
+ ].
- (secondLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (secondLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (secondHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: secondLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (secondHigh := Arg1Reg)].
-
- (firstLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (firstLow := SendNumArgsReg)].
-
- (firstHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh)) bitOr: (self registerMaskFor: firstLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (firstHigh := ClassReg)].
- (((secondLow = ReceiverResultReg or: [secondHigh = ReceiverResultReg]) or: [firstLow = ReceiverResultReg]) or: [firstHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: secondLow secondReg: secondHigh.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: firstLow secondReg: firstHigh.
self ssNativePop: 1.
self SubR: secondLow R: firstLow.
self SubbR: secondHigh R: firstHigh.
self ssPushNativeRegister: firstLow secondRegister: firstHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self SubR: second R: first.
self ssPushNativeRegister: first.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeTruncate32To16 (in category 'inline primitive generators generated code') -----
genLowcodeTruncate32To16
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value |
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self AndCq: 16rFFFF R: value.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeTruncate32To8 (in category 'inline primitive generators generated code') -----
genLowcodeTruncate32To8
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value |
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self AndCq: 16rFF R: value.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeTruncate64To16 (in category 'inline primitive generators generated code') -----
genLowcodeTruncate64To16
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| valueHigh value valueLow |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger2: [:valueLowValue :valueHighValue |
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ ].
- (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (valueLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
- (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
self ssNativePop: 1.
self AndCq: 16rFFFF R: valueLow.
self ssPushNativeRegister: valueLow.
] ifFalse: [
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self AndCq: 16rFFFF R: value.
self ssPushNativeRegister: value.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeTruncate64To32 (in category 'inline primitive generators generated code') -----
genLowcodeTruncate64To32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| valueHigh value valueLow |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger2: [:valueLowValue :valueHighValue |
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ ].
- (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (valueLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
- (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
self ssNativePop: 1.
self ssPushNativeRegister: valueLow.
] ifFalse: [
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self AndCq: 16rFFFFFFFF R: value.
self ssPushNativeRegister: value.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeTruncate64To8 (in category 'inline primitive generators generated code') -----
genLowcodeTruncate64To8
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| valueHigh value valueLow result |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger2ResultInteger: [:valueLowValue :valueHighValue :resultValue |
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ result := resultValue.
+ ].
- (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (valueLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
-
- (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: valueLow)) bitOr: (self registerMaskFor: valueHigh))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (result := SendNumArgsReg)].
- ((valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
self ssNativePop: 1.
self AndCq: 16rFF R: valueLow.
self ssPushNativeRegister: valueLow.
] ifFalse: [
+ self allocateRegistersForLowcodeIntegerResultInteger: [:valueValue :resultValue |
+ value := valueValue.
+ result := resultValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (result := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (result := Arg1Reg)].
- (value = ReceiverResultReg or: [result = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self AndCq: 16rFF R: value.
self ssPushNativeRegister: value.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeUdiv32 (in category 'inline primitive generators generated code') -----
genLowcodeUdiv32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second first |
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self DivR: second R: first Quo: first Rem: second.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeUdiv64 (in category 'inline primitive generators generated code') -----
genLowcodeUdiv64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | secondLow secondHigh firstHigh result resultLow resultHigh first second firstLow |
+ self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :resultValue |
+ second := secondValue.
+ first := firstValue.
+ result := resultValue.
+ ].
- <option: #LowcodeVM> "Lowcode instruction generator"
- | secondLow firstLow secondHigh result resultLow resultHigh first second firstHigh |
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
-
- (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (result := SendNumArgsReg)].
- ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeUint32Great (in category 'inline primitive generators generated code') -----
genLowcodeUint32Great
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second falseJump contJump first |
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpR: second R: first.
falseJump := self JumpBelowOrEqual: 0.
"True result"
self MoveCq: 1 R: first.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: first.
contJump jmpTarget: self Label.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeUint32GreatEqual (in category 'inline primitive generators generated code') -----
genLowcodeUint32GreatEqual
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second falseJump contJump first |
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpR: second R: first.
falseJump := self JumpBelow: 0.
"True result"
self MoveCq: 1 R: first.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: first.
contJump jmpTarget: self Label.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeUint32Less (in category 'inline primitive generators generated code') -----
genLowcodeUint32Less
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second falseJump contJump first |
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpR: second R: first.
falseJump := self JumpAboveOrEqual: 0.
"True result"
self MoveCq: 1 R: first.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: first.
contJump jmpTarget: self Label.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeUint32LessEqual (in category 'inline primitive generators generated code') -----
genLowcodeUint32LessEqual
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second falseJump contJump first |
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self CmpR: second R: first.
falseJump := self JumpAbove: 0.
"True result"
self MoveCq: 1 R: first.
contJump := self Jump: 0.
"False result"
falseJump jmpTarget: self Label.
self MoveCq: 0 R: first.
contJump jmpTarget: self Label.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeUint32ToFloat32 (in category 'inline primitive generators generated code') -----
genLowcodeUint32ToFloat32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value result |
+ self allocateRegistersForLowcodeIntegerResultFloat: [:valueValue :resultValue |
+ value := valueValue.
+ result := resultValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (result := DPFPReg0)].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self ConvertR: value Rs: result.
self ssPushNativeRegisterSingleFloat: result.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeUint32ToFloat64 (in category 'inline primitive generators generated code') -----
genLowcodeUint32ToFloat64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value result |
+ self allocateRegistersForLowcodeIntegerResultFloat: [:valueValue :resultValue |
+ value := valueValue.
+ result := resultValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (result := DPFPReg0)].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self ConvertR: value Rd: result.
self ssPushNativeRegisterDoubleFloat: result.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeUint32ToOop (in category 'inline primitive generators generated code') -----
genLowcodeUint32ToOop
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value |
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self ssFlushAll.
objectRepresentation genLcUInt32ToOop: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeUint64Great (in category 'inline primitive generators generated code') -----
genLowcodeUint64Great
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | secondLow secondHigh firstHigh value first second firstLow |
+ self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :valueValue |
+ second := secondValue.
+ first := firstValue.
+ value := valueValue.
+ ].
- <option: #LowcodeVM> "Lowcode instruction generator"
- | secondLow firstLow secondHigh value first second firstHigh |
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
-
- (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := SendNumArgsReg)].
- ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeUint64GreatEqual (in category 'inline primitive generators generated code') -----
genLowcodeUint64GreatEqual
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | secondLow secondHigh firstHigh value first second firstLow |
+ self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :valueValue |
+ second := secondValue.
+ first := firstValue.
+ value := valueValue.
+ ].
- <option: #LowcodeVM> "Lowcode instruction generator"
- | secondLow firstLow secondHigh value first second firstHigh |
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
-
- (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := SendNumArgsReg)].
- ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeUint64Less (in category 'inline primitive generators generated code') -----
genLowcodeUint64Less
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | secondLow secondHigh firstHigh value first second firstLow |
+ self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :valueValue |
+ second := secondValue.
+ first := firstValue.
+ value := valueValue.
+ ].
- <option: #LowcodeVM> "Lowcode instruction generator"
- | secondLow firstLow secondHigh value first second firstHigh |
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
-
- (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := SendNumArgsReg)].
- ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeUint64LessEqual (in category 'inline primitive generators generated code') -----
genLowcodeUint64LessEqual
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | secondLow secondHigh firstHigh value first second firstLow |
+ self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :valueValue |
+ second := secondValue.
+ first := firstValue.
+ value := valueValue.
+ ].
- <option: #LowcodeVM> "Lowcode instruction generator"
- | secondLow firstLow secondHigh value first second firstHigh |
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
-
- (value := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (value := SendNumArgsReg)].
- ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [value = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeUint64ToFloat32 (in category 'inline primitive generators generated code') -----
genLowcodeUint64ToFloat32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| valueHigh value valueLow result |
+ self allocateRegistersForLowcodeIntegerResultFloat: [:valueValue :resultValue |
+ value := valueValue.
+ result := resultValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (result := DPFPReg0)].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeUint64ToFloat64 (in category 'inline primitive generators generated code') -----
genLowcodeUint64ToFloat64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| valueHigh value valueLow result |
+ self allocateRegistersForLowcodeIntegerResultFloat: [:valueValue :resultValue |
+ value := valueValue.
+ result := resultValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (result := backEnd availableFloatRegisterOrNoneFor: self liveFloatRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredFloatReg: (result := DPFPReg0)].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeUint64ToOop (in category 'inline primitive generators generated code') -----
genLowcodeUint64ToOop
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| valueHigh object value valueLow |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger2ResultOop: [:valueLowValue :valueHighValue :objectValue |
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ object := objectValue.
+ ].
- (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (valueLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
-
- (object := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: valueLow)) bitOr: (self registerMaskFor: valueHigh))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (object := SendNumArgsReg)].
- ((valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) or: [object = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
self ssNativePop: 1.
self ssFlushAll.
objectRepresentation genLcUInt64ToOop: valueLow highPart: valueHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeIntegerResultOop: [:valueValue :objectValue |
+ value := valueValue.
+ object := objectValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (object := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (object := Arg1Reg)].
- (value = ReceiverResultReg or: [object = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self ssFlushAll.
objectRepresentation genLcUInt64ToOop: value.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeUmul32 (in category 'inline primitive generators generated code') -----
genLowcodeUmul32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second first |
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self MulR: second R: first.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeUmul64 (in category 'inline primitive generators generated code') -----
genLowcodeUmul64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | secondLow secondHigh firstHigh result resultLow resultHigh first second firstLow |
+ self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :resultValue |
+ second := secondValue.
+ first := firstValue.
+ result := resultValue.
+ ].
- <option: #LowcodeVM> "Lowcode instruction generator"
- | secondLow firstLow secondHigh result resultLow resultHigh first second firstHigh |
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
-
- (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (result := SendNumArgsReg)].
- ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeUnlockRegisters (in category 'inline primitive generators generated code') -----
genLowcodeUnlockRegisters
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
"Do nothing for now"
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeUnlockVM (in category 'inline primitive generators generated code') -----
genLowcodeUnlockVM
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeUnpin (in category 'inline primitive generators generated code') -----
genLowcodeUnpin
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| object |
+ self allocateRegistersForLowcodeOop: [:objectValue |
+ object := objectValue.
+ ].
- (object := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (object := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- object = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssTop popToReg: object.
self ssPop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeUrem32 (in category 'inline primitive generators generated code') -----
genLowcodeUrem32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second first |
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self DivR: second R: first Quo: second Rem: first.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeUrem64 (in category 'inline primitive generators generated code') -----
genLowcodeUrem64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | secondLow secondHigh firstHigh result resultLow resultHigh first second firstLow |
+ self allocateRegistersForLowcodeInteger2ResultInteger: [:secondValue :firstValue :resultValue |
+ second := secondValue.
+ first := firstValue.
+ result := resultValue.
+ ].
- <option: #LowcodeVM> "Lowcode instruction generator"
- | secondLow firstLow secondHigh result resultLow resultHigh first second firstHigh |
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
-
- (result := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: second)) bitOr: (self registerMaskFor: first))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (result := SendNumArgsReg)].
- ((second = ReceiverResultReg or: [first = ReceiverResultReg]) or: [result = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self abort.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeXor32 (in category 'inline primitive generators generated code') -----
genLowcodeXor32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| second first |
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self XorR: second R: first.
self ssPushNativeRegister: first.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeXor64 (in category 'inline primitive generators generated code') -----
genLowcodeXor64
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
+ | secondLow secondHigh firstHigh first second firstLow |
- <option: #LowcodeVM> "Lowcode instruction generator"
- | secondLow firstLow secondHigh first second firstHigh |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger4: [:secondLowValue :secondHighValue :firstLowValue :firstHighValue |
+ secondLow := secondLowValue.
+ secondHigh := secondHighValue.
+ firstLow := firstLowValue.
+ firstHigh := firstHighValue.
+ ].
- (secondLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (secondLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (secondHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: secondLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (secondHigh := Arg1Reg)].
-
- (firstLow := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (firstLow := SendNumArgsReg)].
-
- (firstHigh := backEnd availableRegisterOrNoneFor: (((self liveRegisters bitOr: (self registerMaskFor: secondLow)) bitOr: (self registerMaskFor: secondHigh)) bitOr: (self registerMaskFor: firstLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (firstHigh := ClassReg)].
- (((secondLow = ReceiverResultReg or: [secondHigh = ReceiverResultReg]) or: [firstLow = ReceiverResultReg]) or: [firstHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: secondLow secondReg: secondHigh.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: firstLow secondReg: firstHigh.
self ssNativePop: 1.
self XorR: secondLow R: firstLow.
self XorR: secondHigh R: firstHigh.
self ssPushNativeRegister: firstLow secondRegister: firstHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeInteger2: [:secondValue :firstValue |
+ second := secondValue.
+ first := firstValue.
+ ].
- (second := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (second := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (first := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: second))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (first := Arg1Reg)].
- (second = ReceiverResultReg or: [first = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: second.
self ssNativePop: 1.
self ssNativeTop nativePopToReg: first.
self ssNativePop: 1.
self XorR: second R: first.
self ssPushNativeRegister: first.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeZeroExtend32From16 (in category 'inline primitive generators generated code') -----
genLowcodeZeroExtend32From16
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value |
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self ZeroExtend16R: value R: value.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeZeroExtend32From8 (in category 'inline primitive generators generated code') -----
genLowcodeZeroExtend32From8
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| value |
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self ZeroExtend8R: value R: value.
self ssPushNativeRegister: value.
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeZeroExtend64From16 (in category 'inline primitive generators generated code') -----
genLowcodeZeroExtend64From16
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| valueHigh value valueLow |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger2: [:valueLowValue :valueHighValue |
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ ].
- (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (valueLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
- (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
self ssNativePop: 1.
self ZeroExtend16R: valueLow R: valueLow.
self MoveCq: 0 R: valueHigh.
self ssPushNativeRegister: valueLow secondRegister: valueHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self ZeroExtend16R: value R: value.
self ssPushNativeRegister: value.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeZeroExtend64From32 (in category 'inline primitive generators generated code') -----
genLowcodeZeroExtend64From32
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| resultLow resultHigh value result |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeIntegerResultInteger2: [:valueValue :resultLowValue :resultHighValue |
+ value := valueValue.
+ resultLow := resultLowValue.
+ resultHigh := resultHighValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (resultLow := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (resultLow := Arg1Reg)].
-
- (resultHigh := backEnd availableRegisterOrNoneFor: ((self liveRegisters bitOr: (self registerMaskFor: value)) bitOr: (self registerMaskFor: resultLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (resultHigh := SendNumArgsReg)].
- ((value = ReceiverResultReg or: [resultLow = ReceiverResultReg]) or: [resultHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self MoveR: value R: resultLow.
self MoveCq: 0 R: resultHigh.
self ssPushNativeRegister: resultLow secondRegister: resultHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeIntegerResultInteger: [:valueValue :resultValue |
+ value := valueValue.
+ result := resultValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (result := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: value))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (result := Arg1Reg)].
- (value = ReceiverResultReg or: [result = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self ZeroExtend32R: value R: value.
self ssPushNativeRegister: value.
].
^ 0
!
Item was changed:
----- Method: StackToRegisterMappingCogit>>genLowcodeZeroExtend64From8 (in category 'inline primitive generators generated code') -----
genLowcodeZeroExtend64From8
+ <option: #LowcodeVM>
+ <inline: true>
+ "Generated by the Lowcode instruction generator."
- <option: #LowcodeVM> "Lowcode instruction generator"
| valueHigh value valueLow |
BytesPerWord = 4 ifTrue: [
+ self allocateRegistersForLowcodeInteger2: [:valueLowValue :valueHighValue |
+ valueLow := valueLowValue.
+ valueHigh := valueHighValue.
+ ].
- (valueLow := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (valueLow := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
-
- (valueHigh := backEnd availableRegisterOrNoneFor: (self liveRegisters bitOr: (self registerMaskFor: valueLow))) = NoReg ifTrue:
- [self ssAllocateRequiredReg: (valueHigh := Arg1Reg)].
- (valueLow = ReceiverResultReg or: [valueHigh = ReceiverResultReg]) ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: valueLow secondReg: valueHigh.
self ssNativePop: 1.
self ZeroExtend8R: valueLow R: valueLow.
self MoveCq: 0 R: valueHigh.
self ssPushNativeRegister: valueLow secondRegister: valueHigh.
] ifFalse: [
+ self allocateRegistersForLowcodeInteger: [:valueValue |
+ value := valueValue.
+ ].
- (value := backEnd availableRegisterOrNoneFor: self liveRegisters) = NoReg ifTrue:
- [self ssAllocateRequiredReg:
- (value := optStatus isReceiverResultRegLive
- ifTrue: [Arg0Reg]
- ifFalse: [ReceiverResultReg])].
- value = ReceiverResultReg ifTrue:
- [ optStatus isReceiverResultRegLive: false ].
self ssNativeTop nativePopToReg: value.
self ssNativePop: 1.
self ZeroExtend8R: value R: value.
self ssPushNativeRegister: value.
].
^ 0
!
Item was added:
+ ----- Method: StackToRegisterMappingCogit>>ssNativeValue: (in category 'simulation stack') -----
+ ssNativeValue: n
+ <returnTypeC: #'CogSimStackNativeEntry *'>
+ <option: #LowcodeVM>
+ ^self simNativeStackAt: simStackPtr - n!
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