[Vm-dev] VM Maker: VMMaker.oscog-eem.2336.mcz

commits at source.squeak.org commits at source.squeak.org
Tue Feb 20 21:38:08 UTC 2018


Eliot Miranda uploaded a new version of VMMaker to project VM Maker:
http://source.squeak.org/VMMaker/VMMaker.oscog-eem.2336.mcz

==================== Summary ====================

Name: VMMaker.oscog-eem.2336
Author: eem
Time: 20 February 2018, 1:37:39.077638 pm
UUID: 9f7b71dd-9980-4005-b64e-0bbf8cda761e
Ancestors: VMMaker.oscog-eem.2335

RegisterAllocatingCogit:
Fix the visited register filter in the register swapper in the merge engine.
Write some regression tests for the merge engine.

It appears that the new release process proceeds with the RegisterAllocatingCogit.

=============== Diff against VMMaker.oscog-eem.2335 ===============

Item was added:
+ ----- Method: Cogit>>opcodePrintStringFrom:to: (in category 'debug printing') -----
+ opcodePrintStringFrom: startIndex to: stopIndex
+ 	^(String streamContents:
+ 		[:s|
+ 		startIndex to: stopIndex do:
+ 			[:i|
+ 			(abstractOpcodes at: i) printStateOn: s]]) allButFirst!

Item was changed:
  ----- Method: RegisterAllocatingCogit>>resolveConflicts:with:to: (in category 'bytecode generator support') -----
  resolveConflicts: registersInCommon with: mergeSimStack to: simStackPtr
  	"registersInCommon is the register mask of registers in use in both the current
  	 simStack and the target mergeSimStack. Swap any and all conflicting register uses
  	 in registersInCommon, until register uses in simStack agree with mergeSimStack."
+ 	| registerExchanges registerLocations agreements visited initialIndex initialStack |
- 	| registerExchanges registerLocations agreements visited initialIndex |
  	"registerLocations records where a register has moved to
  	 during an exchange. This allows a single pass of the stack
  	 to rename registers, instead of 1/2 N^2; max stack ~ 56"
  	<var: 'registerExchanges' declareC: 'int registerExchanges[NumRegisters]'>
  	<var: 'registerLocations' declareC: 'int registerLocations[NumRegisters]'>
  	self deny: self duplicateRegisterAssignmentsInTemporaries.
  	registersInCommon = (self registerMaskFor: FPReg) ifTrue:
  		[self assert: (self conflictsResolvedBetweenSimStackAnd: mergeSimStack).
  		 ^self].
  	self cCode: '' inSmalltalk:
  		[registerExchanges := CArrayAccessor on: (Array new: NumRegisters).
  		 registerLocations := CArrayAccessor on: (Array new: NumRegisters)].
  	0 to: NumRegisters - 1 do:
  		[:i| registerExchanges at: i put: i].
+ 	self cCode: '' inSmalltalk:
+ 		[initialIndex := opcodeIndex. initialStack := self simStackPrintString]. "for debugging"
- 	initialIndex := opcodeIndex. "for debugging"
  	agreements := visited := 0.
  	0 to: simStackPtr do:
  		[:i| | currentReg targetReg |
  		currentReg := (self simStackAt: i) registerOrNone.
  		targetReg := (self simStack: mergeSimStack at: i) registerOrNone.
  		(currentReg ~= NoReg
  		 and: [targetReg ~= NoReg]) ifTrue:
  			[currentReg := registerExchanges at: currentReg.
  			 currentReg = targetReg
  				ifTrue:
  					[(self register: currentReg isInMask: visited) ifFalse:
  						[visited := visited bitOr: (self registerMaskFor: currentReg).
  						 agreements := agreements bitOr: (self registerMaskFor: currentReg)]]
  				ifFalse:
  					[((self register: currentReg isInMask: registersInCommon)
+ 					  and: [self register: currentReg isNotInMask: (visited bitOr: agreements)]) ifTrue:
- 					  and: [(self register: currentReg isNotInMask: visited)
- 							or: [self register: targetReg isNotInMask: visited]]) ifTrue:
  						[| this that |
  						 visited := visited bitOr: (self registerMaskFor: currentReg and: targetReg).
  						 self SwapR: targetReg R: currentReg Scratch: RISCTempReg.
  						 this := registerExchanges at: currentReg.
  						 that := registerExchanges at: targetReg.
  						 registerExchanges
  							at: currentReg put: that;
  							at: targetReg put: this]]]].
  	(visited := visited bitClear: agreements) = 0 ifTrue:
  		[self assert: (self conflictsResolvedBetweenSimStackAnd: mergeSimStack).
  		 ^self].
  	0 to: NumRegisters - 1 do:
  		[:i| registerLocations at: (registerExchanges at: i) put: i].
  	0 to: simStackPtr do:
  		[:i| | ssEntry reg |
  		ssEntry := self simStackAt: i.
  		reg := ssEntry registerOrNone.
  		(reg ~= NoReg
  		 and: [(self register: reg isInMask: registersInCommon)
  		 and: [reg ~= (self simStack: mergeSimStack at: i) registerOrNone]]) ifTrue:
  			[ssEntry type = SSRegister
  				ifTrue: [ssEntry register: (registerLocations at: reg)]
  				ifFalse: [ssEntry liveRegister: (registerLocations at: reg)]]].
  	self deny: self duplicateRegisterAssignmentsInTemporaries.
  	self assert: (self conflictsResolvedBetweenSimStackAnd: mergeSimStack)
  	"(initialIndex to: opcodeIndex - 1) collect: [:x| abstractOpcodes at: x]"!

Item was added:
+ TestCase subclass: #RegisterAllocatingCogitTests
+ 	instanceVariableNames: ''
+ 	classVariableNames: ''
+ 	poolDictionaries: 'CogAbstractRegisters'
+ 	category: 'VMMaker-Tests'!

Item was added:
+ ----- Method: RegisterAllocatingCogitTests>>testMergeRegisterSwappingForX64InBlockNodeAnalysis (in category 'tests') -----
+ testMergeRegisterSwappingForX64InBlockNodeAnalysis
+ 	"Test the first merge in BlockNode>>#analyseTempsWithin:rootNode:assignmentPools:"
+ 	"self new testMergeRegisterSwappingForX64InBlockNodeAnalysis"
+ 	| cogit fixup start |
+ 	cogit := self x64Cogit.
+ 	cogit
+ 		instVarNamed: 'methodOrBlockNumArgs' put: 3;
+ 		instVarNamed: 'methodOrBlockNumTemps' put: 5;
+ 		initSimStackForFramefulMethod: nil.
+ 	(cogit simStackAt: 0) liveRegister: ReceiverResultReg.
+ 	(cogit simStackAt: 1) liveRegister: Extra4Reg.
+ 	(cogit simStackAt: 5) liveRegister: Extra5Reg.
+ 	cogit ssPushDesc: (cogit simStackAt: 1).
+ 	(fixup := cogit bytecodeFixupClass for: cogit)
+ 		mergeSimStack: cogit copySimStack;
+ 		simStackPtr: (cogit instVarNamed: 'simStackPtr');
+ 		becomeMergeFixup.
+ 	cogit
+ 		ssPop: 1;
+ 		ssPushDesc: (cogit simStackAt: 0).
+ 	(cogit simStackAt: 1) liveRegister: NoReg.
+ 	(cogit simStackAt: 5) liveRegister: Extra5Reg.
+ 
+ 	self assert: '
+ 0		(bo FPReg-24 (spilled) (live: ReceiverResultReg))
+ 1		(bo FPReg+32 (spilled))
+ 2		(bo FPReg+24 (spilled))
+ 3		(bo FPReg+16 (spilled))
+ 4		(bo FPReg-32 (spilled))
+ 5		(bo FPReg-40 (spilled) (live: Extra5Reg))
+ 6<-(sb)	(bo FPReg-24 (live: ReceiverResultReg))
+ '		 equals: cogit simStackPrintString.
+ 	self assert:'
+ 0		(bo FPReg-24 (spilled) (live: ReceiverResultReg))
+ 1		(bo FPReg+32 (spilled) (live: Extra4Reg))
+ 2		(bo FPReg+24 (spilled))
+ 3		(bo FPReg+16 (spilled))
+ 4		(bo FPReg-32 (spilled))
+ 5		(bo FPReg-40 (spilled) (live: Extra5Reg))
+ 6<-		(bo FPReg+32 (live: Extra4Reg))
+ '		equals: fixup simStackPrintString.
+ 
+ 	start := cogit getOpcodeIndex.
+ 	[cogit mergeCurrentSimStackWith: fixup]
+ 		on: AssertionFailure
+ 		do: [:ex|
+ 			self assert: false description: 'assertion failure in cogit'.
+ 			ex resume: nil].
+ 
+ 	self assert: '
+ 0		(bo FPReg-24 (spilled) (live: ReceiverResultReg))
+ 1		(bo FPReg+32 (spilled))
+ 2		(bo FPReg+24 (spilled))
+ 3		(bo FPReg+16 (spilled))
+ 4		(bo FPReg-32 (spilled))
+ 5		(bo FPReg-40 (spilled) (live: Extra5Reg))
+ 6<-(sb)	(spill @ FPReg-48 (live: Extra4Reg))
+ '		 equals: cogit simStackPrintString.
+ 
+ 	self assert:  '(MoveRR ReceiverResultReg Extra4Reg)'
+ 		equals: (cogit opcodePrintStringFrom: start to: cogit getOpcodeIndex - 1)!

Item was added:
+ ----- Method: RegisterAllocatingCogitTests>>testMergeRegisterSwappingForX64InSmallIntegerPrinting (in category 'tests') -----
+ testMergeRegisterSwappingForX64InSmallIntegerPrinting
+ 	"self new testMergeRegisterSwappingForX64InSmallIntegerPrinting"
+ 	| cogit fixup start |
+ 	cogit := self x64Cogit.
+ 	cogit
+ 		instVarNamed: 'methodOrBlockNumArgs' put: 4;
+ 		instVarNamed: 'methodOrBlockNumTemps' put: 9;
+ 		initSimStackForFramefulMethod: nil;
+ 		ssPushConstant: (cogit objectMemory integerObjectOf: 0).
+ 	(fixup := cogit bytecodeFixupClass for: cogit)
+ 		mergeSimStack: cogit copySimStack;
+ 		simStackPtr: (cogit instVarNamed: 'simStackPtr');
+ 		becomeMergeFixup.
+ 	(cogit simStackAt: 0) liveRegister: Extra5Reg.
+ 	(cogit simStackAt: 5) liveRegister: Extra4Reg.
+ 	(cogit simStackAt: 7) liveRegister: Extra3Reg.
+ 	(cogit simStack: fixup mergeSimStack at: 10) constant: (cogit objectMemory integerObjectOf: 1).
+ 	(cogit simStack: fixup mergeSimStack at: 5) liveRegister: Extra5Reg.
+ 	(cogit simStack: fixup mergeSimStack at: 7) liveRegister: Extra4Reg.
+ 	(cogit simStack: fixup mergeSimStack at: 10) liveRegister: Extra3Reg.
+ 
+ 	self assert: '
+ 0		(bo FPReg-24 (spilled) (live: Extra5Reg))
+ 1		(bo FPReg+40 (spilled))
+ 2		(bo FPReg+32 (spilled))
+ 3		(bo FPReg+24 (spilled))
+ 4		(bo FPReg+16 (spilled))
+ 5		(bo FPReg-32 (spilled) (live: Extra4Reg))
+ 6		(bo FPReg-40 (spilled))
+ 7		(bo FPReg-48 (spilled) (live: Extra3Reg))
+ 8		(bo FPReg-56 (spilled))
+ 9		(bo FPReg-64 (spilled))
+ 10<-(sb)	(const =0 (16r0))
+ '		 equals: cogit simStackPrintString.
+ 	self assert: '
+ 0		(bo FPReg-24 (spilled))
+ 1		(bo FPReg+40 (spilled))
+ 2		(bo FPReg+32 (spilled))
+ 3		(bo FPReg+24 (spilled))
+ 4		(bo FPReg+16 (spilled))
+ 5		(bo FPReg-32 (spilled) (live: Extra5Reg))
+ 6		(bo FPReg-40 (spilled))
+ 7		(bo FPReg-48 (spilled) (live: Extra4Reg))
+ 8		(bo FPReg-56 (spilled))
+ 9		(bo FPReg-64 (spilled))
+ 10<-		(const =1 (16r1) (live: Extra3Reg))
+ '		equals: fixup simStackPrintString.
+ 
+ 	start := cogit getOpcodeIndex.
+ 	[cogit mergeCurrentSimStackWith: fixup]
+ 		on: AssertionFailure
+ 		do: [:ex|
+ 			self assert: false description: 'assertion failure in cogit'.
+ 			ex resume: nil].
+ 
+ 	self assert: '
+ 0		(bo FPReg-24 (spilled))
+ 1		(bo FPReg+40 (spilled))
+ 2		(bo FPReg+32 (spilled))
+ 3		(bo FPReg+24 (spilled))
+ 4		(bo FPReg+16 (spilled))
+ 5		(bo FPReg-32 (spilled) (live: Extra5Reg))
+ 6		(bo FPReg-40 (spilled))
+ 7		(bo FPReg-48 (spilled) (live: Extra4Reg))
+ 8		(bo FPReg-56 (spilled))
+ 9		(bo FPReg-64 (spilled))
+ 10<-(sb)	(reg Extra3Reg)
+ '		 equals: cogit simStackPrintString.
+ 
+ 	self assert:  '(XCHGRR 15 14) (XCHGRR 14 13) (MoveCqR 1 Extra3Reg)'
+ 		equals: (cogit opcodePrintStringFrom: start to: cogit getOpcodeIndex - 1)!

Item was added:
+ ----- Method: RegisterAllocatingCogitTests>>x64Cogit (in category 'private') -----
+ x64Cogit
+ 	^RegisterAllocatingCogit initializedInstanceForTests: #(ObjectMemory Spur64BitCoMemoryManager
+ 															ISA X64
+ 															MULTIPLEBYTECODESETS true)!

Item was added:
+ ----- Method: SimpleStackBasedCogit>>register:and:isNotInMask: (in category 'testing') -----
+ register: reg1 and: reg2 isNotInMask: mask
+ 	<inline: true>
+ 	^mask noMask: (self registerMaskFor: reg1 and: reg2)!

Item was changed:
+ ----- Method: SimpleStackBasedCogit>>register:isInMask: (in category 'testing') -----
- ----- Method: SimpleStackBasedCogit>>register:isInMask: (in category 'simulation stack') -----
  register: reg isInMask: mask
  	<inline: true>
  	^ mask anyMask: (self registerMaskFor: reg)!

Item was changed:
+ ----- Method: SimpleStackBasedCogit>>register:isNotInMask: (in category 'testing') -----
- ----- Method: SimpleStackBasedCogit>>register:isNotInMask: (in category 'simulation stack') -----
  register: reg isNotInMask: mask
  	<inline: true>
  	^ mask noMask: (self registerMaskFor: reg)!



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