[Vm-dev] VM Maker: CogPools-ISAs-eem.6.mcz

[commits at source.squeak.org]

Eliot Miranda uploaded a new version of CogPools-ISAs to project VM Maker:
http://source.squeak.org/VMMaker/CogPools-ISAs-eem.6.mcz

==================== Summary ====================

Name: CogPools-ISAs-eem.6
Author: eem
Time: 18 December 2019, 1:05:42.560276 am
UUID: 3c1e51f3-ec07-4453-a8be-d455a8791ca7
Ancestors: CogPools-ISAs-eem.5

A64; Make the other arm in extractOffsetFromLoadStore: correct (for imm9).
Make instructionIsPCRelativeLoad: match CogARMv8Compiler's implementation.

=============== Diff against CogPools-ISAs-eem.5 ===============

Item was changed:
  ----- Method: ARMv8A64Opcodes class>>extractOffsetFromLoadStore: (in category 'accessing') -----
  extractOffsetFromLoadStore: word
  	"C4.1.4	Loads and Stores	C4-266
  
  	 Table C4-5 Encoding table for the Loads and Stores group
  
  	 LDAPR/STLR (unscaled immediate) on page C4-279			signed imm9 12 - 20
  	 Load/store register (unscaled immediate) on page C4-283		signed imm9 12 - 20
  	 Load/store register (immediate post-indexed) on page C4-284	signed imm9 12 - 20
  	 Load/store register (immediate pre-indexed) on page C4-286	signed imm9 12 - 20
  	 Load/store register (pac) on page C4-297						signed imm9 12 - 20
  	 Load/store register (unsigned immediate) on page C4-297		unsigned imm12 21 - 10"
  	^(word >> 23 bitAnd: 2r001110110) = 2r001110010 "op0 = xx11, b27=1, b25=0, op2 = 1x"
  		ifTrue: [(word >> 10 bitAnd: 1 << 12 - 1) bitShift: word >> 30]
+ 		ifFalse: [(word >> 12 bitAnd: 1 << 9 - 1) - (word >> 11 bitAnd: 1 << 9)]!
- 		ifFalse: [self halt. (word >> 12 bitAnd: 1 << 9 - 1) - (word >> 10 bitAnd: 1 << 19)]!

Item was changed:
  ----- Method: ARMv8A64Opcodes class>>instructionIsPCRelativeLoad: (in category 'testing') -----
  instructionIsPCRelativeLoad: word
  	"C4.1		A64 instruction set encoding on page	C4-252
  	 C4.1.4		Loads and Stores						C4-266"
  						"op0,b27,b25,op2" "op0=xx01,b27=1,b25=0,op2=0x"
+ 	^(word >> 24 bitAnd: 2r10111111) = 2r00011000!
- 	^(word >> 23 bitAnd: 2r1110110) = 2r110000!