[Vm-dev] VM Maker: Cog-eem.365.mcz

commits at source.squeak.org commits at source.squeak.org
Tue Nov 19 23:49:06 UTC 2019

Eliot Miranda uploaded a new version of Cog to project VM Maker:

==================== Summary ====================

Name: Cog-eem.365
Author: eem
Time: 19 November 2019, 3:49:04.530649 pm
UUID: e04c4d6e-a56a-4ddf-a538-dcba09fc3d8b
Ancestors: Cog-eem.364

Include the coprocessor control and nextpc registers in printing, & state access.

=============== Diff against Cog-eem.364 ===============

Item was changed:
  CogProcessorAlien variableByteSubclass: #GdbARMv8Alien
  	instanceVariableNames: ''
  	classVariableNames: 'BadCPUInstance ExecutionError InstructionPrefetchError MemorBoundsError NoError PanicError SomethingLoggedError UnsupportedOperationError'
  	poolDictionaries: ''
  	category: 'Cog-Processors'!
+ !GdbARMv8Alien commentStamp: 'eem 11/19/2019 15:39' prior: 0!
+ I am a wrapper around the struct sim aarch64 CPU instance and emulator routines and I give access to disassembling using libopcodes.!

Item was changed:
  ----- Method: GdbARMv8Alien>>printRegisterState:on: (in category 'printing') -----
  printRegisterState: registerStateVector on: aStream
  	self printFields: #(	r0 r1 r2 r3 cr
  						r4 r5 r6 r7 cr
  						r8 r9 r10 r11 cr
  						r12 r13 r14 r15 cr
  						r16 r17 r18 r19 cr
  						r20 r21 r22 r23 cr
  						r24 r25 r26 r27 cr
  						r28 fp lr sp cr
  						d0 d1 d2 d3 cr
  						d4 d5 d6 d7 cr
  						d8 d9 d10 d11 cr
  						d12 d13 d14 d15 cr
  						d16 d17 d18 d19 cr
  						d20 d21 d22 d23 cr
  						d24 d25 d26 d27 cr
  						d28 d29 d30 d31 cr
+ 						pc CPSR FPSR FPCR nextpc cr)
- 						pc cr)
  		inRegisterState: registerStateVector
  		on: aStream!

Item was changed:
  ----- Method: GdbARMv8Alien>>registerState (in category 'accessing-abstract') -----
  	^{	self r0. self r1. self r2. self r3. self r4. self r5. self r6. self r7.
  		self r8. self r9. self r10. self r11. self r12. self r13. self r14. self r15.
  		self r16. self r17. self r18. self r19. self r20. self r21. self r22. self r23.
  		self r24. self r25. self r26. self r27. self r28. self fp. self lr. self sp.
  		self d0. self d1. self d2. self d3. self d4. self d5. self d6. self d7.
  		self d8. self d9. self d10. self d11. self d12. self d13. self d14. self d15.
  		self d16. self d17. self d18. self d19. self d20. self d21. self d22. self d23.
  		self d24. self d25. self d26. self d27. self d28. self d29. self d30. self d31.
+ 		self pc. self rawCPSR. self fpCPSR. self fpCPCR. self nextpc }!
- 		self pc }!

Item was changed:
  ----- Method: GdbARMv8Alien>>registerStateGetters (in category 'accessing-abstract') -----
  	^#(r0 r1 r2 r3 r4 r5 r6 r7
  		r8 r9 r10 r11 r12 r13 r14 r15
  		r16 r17 r18 r19 r20 r21 r22 r23
  		r24 r25 r26 r27 r28 fp lr sp
  		d0 d1 d2 d3 d4 d5 d6 d7
  		d8 d9 d10 d11 d12 d13 d14 d15
  		d16 d17 d18 d19 d20 d21 d22 d23
  		d24 d25 d26 d27 d28 d29 d30 d31
+ 		pc rawCPSR fpCPSR fpCPCR nextpc)!
- 		pc rawCPSR FPSR FPCR nextpc)!

Item was changed:
  ----- Method: GdbARMv8Alien>>registerStateSetters (in category 'accessing-abstract') -----
  	^#(r0: r1: r2: r3: r4: r5: r6: r7:
  		r8: r9: r10: r11: r12: r13: r14: r15:
  		r16: r17: r18: r19: r20: r21: r22: r23:
  		r24: r25: r26: r27: r28: fp: lr: sp:
  		d0: d1: d2: d3: d4: d5: d6: d7:
  		d8: d9: d10: d11: d12: d13: d14: d15:
  		d16: d17: d18: d19: d20: d21: d22: d23:
  		d24: d25: d26: d27: d28: d29: d30: d31:
+ 		pc:  rawCPSR: fpCPSR: fpCPCR: nextpc:)!
- 		pc:  rawCPSR: FPSR: FPCR: nextpc:)!

Item was changed:
  GdbARMv8Alien variableByteSubclass: #GdbARMv8Alien64
  	instanceVariableNames: ''
  	classVariableNames: ''
  	poolDictionaries: ''
  	category: 'Cog-Processors'!
+ !GdbARMv8Alien64 commentStamp: 'eem 11/19/2019 15:39' prior: 0!
+ I am a wrapper around the struct sim aarch64 CPU instance and emulator routines when compiled for 64-bits. I give access to disassembling using libopcodes.!

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