[Vm-dev] [Cuis-dev] Cuis on a RISC
tim Rowledge
tim at rowledge.org
Wed Jun 15 17:22:06 UTC 2022
I could have sworn I've read emails from someone that did a MIPS cog port, but it hasn't made it to the 'official' opensmalltalk-vm repository as yet.
A complication for a RiscV cog that I would anticipate from my fairly limited reading on RiscV is that the actual instruction set for any particular cpu can vary quite a lot because of the building-block nature of the specification. I hope it's not quite as confusing as it seems to me so far.
> On 2022-06-15, at 5:59 AM, ken.dickey at whidbey.com wrote:
>
> On 2022-06-15 03:06, Gerald Klix via Cuis-dev wrote:
>
>> Nevertheless I don't understand Ken's answer.
>
>> To make a story too long short: Obviously there never was a JIT version of the
>> opensmalltalk VM for the RiscV-architecture (I don't know to state this in a more explicit way).
>
> Gerald,
>
> Sorry to be confusing.
>
> OpenSmalltalk-VM has many delivery targets.
> OSs: Windows, Linux, MacOS, SunOS. [?RiscOS?]
Ah. RISC OS. Yes, well, I haven't had any time to update that in quite a while. I really would like to do a cog version since we have the ARM cog already sorted, but *time*. What even is that thing *spare time*?
> CPU Architectures: Intel, Arm, now Risc-V
> 32 bit, 64 bit variants
> Displays & plugins
> [X-Windows, FrameBuffer, ..]
>
> There are three basic VM "flavors"
> Original stack VM ["Back to the Future"]
> Spur [Stack VM with top of stack mapped to machine registers]
> a.k.s. squeak.stack.spur
> Cog [Above + JIT]
> a.k.a. squeak.cog.spur
>
> The VM easiest to port is squeak.stack.spur
>
> The squeak.stack.spur flavor is running now on RISC-V RV64 (64 bit) Debian Linux.
>
> No JIT (no squeak,cog.spur) yet.
>
> HTH,
> -KenD
>
tim
--
tim Rowledge; tim at rowledge.org; http://www.rowledge.org/tim
Strange OpCodes: SDP: Search and Destroy Pointer
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