[Vm-dev] Cuis on a RISC

[Jecel Assumpcao Jr]

I would like to point out that the J Extension for RISC-V is still being
defined. It is meant for Java, Javascript and other managed languages,
so the OpenSmalltalk VM would certainly qualify.

Since it is not finished, no current RISC-V implements it yet. And it
might not be a popular option even when available. That means that a
virtual machine can't count on it and if it runs on non RISC-V
processors will have to consider it an option in any case.

So far two items have been worked on: pointer masking and instruction
cache coherence.

Pointer masking adds two control registers (optionally per priviledge
level) such that any address has its bits indicated by the first
register replaced by the corresponding bits in the second register.
Something like

effectiveAddress := (mask not and: address) or: (mask and: base)

This allows the same functionality as extensions for other processors,
such as TBI (top byte ignore) for ARM, UAI (upper address ignore) for
AMD x86-64 and LAM (linear address masking) for Intel x86-64. It also
gives hardware support to some stuff that is now done very awkwardly in
software.

The normal RISC-V memory model supposed cache coherence for the data
caches, but makes the software deal with the instruction caches. That is
a problem if you are running a JIT computer on one processor which is
patching code used by other processors. This can be very tricky on
processors like RISC-V which need a pair of instructions to jump to a
random location.

If there are any suggestions of things that can be done to make
Smalltalk virtual machines work better on RISC-V I would be glad to pass
them to the group. I posted some ideas here back in 2018.

-- Jecel