<div dir="ltr">Ok this fix the bug the SistaCogit now runs fine.<div><br></div><div>It could be better to put some values on stack instead of using registers when calling some trampolines but I am a bit confused by which registers a trampoline can used in its implementation so I postpone that for later.</div></div><div class="gmail_extra"><br><div class="gmail_quote">2015-05-05 11:48 GMT+02:00 <span dir="ltr"><<a href="mailto:commits@source.squeak.org" target="_blank">commits@source.squeak.org</a>></span>:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br>
Eliot Miranda uploaded a new version of VMMaker to project VM Maker:<br>
<a href="http://source.squeak.org/VMMaker/VMMaker.oscog-cb.1283.mcz" target="_blank">http://source.squeak.org/VMMaker/VMMaker.oscog-cb.1283.mcz</a><br>
<br>
==================== Summary ====================<br>
<br>
Name: VMMaker.oscog-cb.1283<br>
Author: cb<br>
Time: 5 May 2015, 11:48:13.804 am<br>
UUID: 3000cd43-f84f-4b75-9fdf-aff579a5105b<br>
Ancestors: VMMaker.oscog-eem.1282<br>
<br>
Fixed a bug in SistaCogit where a trampoline needed a specific register instead of an allocated one.<br>
<br>
=============== Diff against VMMaker.oscog-eem.1282 ===============<br>
<br>
Item was removed:<br>
- ----- Method: SistaStackToRegisterMappingCogit>>allocateRegPreferringCalleeSavedNotConflictingWith: (in category 'simulation stack') -----<br>
- allocateRegPreferringCalleeSavedNotConflictingWith: regMask<br>
- "If there are multiple free registers, choose one which is callee saved,<br>
- else just allocate a register not conflicting with regMask"<br>
- | reg |<br>
- reg := backEnd availableRegisterOrNilFor: ((self liveRegisters bitOr: regMask) bitOr: callerSavedRegMask).<br>
- ^ reg<br>
- ifNil: [ self allocateRegNotConflictingWith: regMask ]<br>
- ifNotNil: [ reg ]!<br>
<br>
Item was changed:<br>
----- Method: SistaStackToRegisterMappingCogit>>genJumpIf:to: (in category 'bytecode generator support') -----<br>
genJumpIf: boolean to: targetBytecodePC<br>
"The heart of performance counting in Sista. Conditional branches are 6 times less<br>
frequent than sends and can provide basic block frequencies (send counters can't).<br>
Each conditional has a 32-bit counter split into an upper 16 bits counting executions<br>
and a lower half counting untaken executions of the branch. Executing the branch<br>
decrements the upper half, tripping if the count goes negative. Not taking the branch<br>
decrements the lower half. N.B. We *do not* eliminate dead branches (true ifTrue:/true ifFalse:)<br>
so that scanning for send and branch data is simplified and that branch data is correct."<br>
<inline: false><br>
+ | desc ok counterAddress countTripped retry |<br>
- | desc ok counterAddress countTripped retry counterReg |<br>
<var: #ok type: #'AbstractInstruction *'><br>
<var: #desc type: #'CogSimStackEntry *'><br>
<var: #retry type: #'AbstractInstruction *'><br>
<var: #countTripped type: #'AbstractInstruction *'><br>
<br>
(coInterpreter isOptimizedMethod: methodObj) ifTrue: [ ^ super genJumpIf: boolean to: targetBytecodePC ].<br>
<br>
self ssFlushTo: simStackPtr - 1.<br>
desc := self ssTop.<br>
self ssPop: 1.<br>
desc popToReg: TempReg.<br>
<br>
+ "We need SendNumArgsReg because of the mustBeBooleanTrampoline"<br>
+ self ssAllocateRequiredReg: SendNumArgsReg.<br>
+<br>
- "We prefer calleeSaved to avoid saving it across the trap trip trampoline"<br>
- counterReg := self allocateRegPreferringCalleeSavedNotConflictingWith: 0.<br>
retry := self Label.<br>
self<br>
genExecutionCountLogicInto: [ :cAddress :countTripBranch |<br>
counterAddress := cAddress.<br>
countTripped := countTripBranch ]<br>
+ counterReg: SendNumArgsReg.<br>
- counterReg: counterReg.<br>
counterIndex := counterIndex + 1.<br>
<br>
"Cunning trick by LPD. If true and false are contiguous subtract the smaller.<br>
Correct result is either 0 or the distance between them. If result is not 0 or<br>
their distance send mustBeBoolean."<br>
self assert: (objectMemory objectAfter: objectMemory falseObject) = objectMemory trueObject.<br>
self annotate: (self SubCw: boolean R: TempReg) objRef: boolean.<br>
self JumpZero: (self ensureFixupAt: targetBytecodePC - initialPC).<br>
<br>
+ self genFallsThroughCountLogicCounterReg: SendNumArgsReg counterAddress: counterAddress.<br>
- self genFallsThroughCountLogicCounterReg: counterReg counterAddress: counterAddress.<br>
<br>
self CmpCq: (boolean == objectMemory falseObject<br>
ifTrue: [objectMemory trueObject - objectMemory falseObject]<br>
ifFalse: [objectMemory falseObject - objectMemory trueObject])<br>
R: TempReg.<br>
ok := self JumpZero: 0.<br>
+ self MoveCq: 0 R: SendNumArgsReg. "if counterReg is 0 this is a mustBeBoolean, not a counter trip."<br>
- self MoveCq: 0 R: counterReg. "if counterReg is 0 this is a mustBeBoolean, not a counter trip."<br>
<br>
countTripped jmpTarget:<br>
(self CallRT: (boolean == objectMemory falseObject<br>
ifTrue: [ceSendMustBeBooleanAddFalseTrampoline]<br>
ifFalse: [ceSendMustBeBooleanAddTrueTrampoline])).<br>
<br>
"If we're in an image which hasn't got the Sista code loaded then the ceCounterTripped:<br>
trampoline will return directly to machine code, returning the boolean. So the code should<br>
jump back to the retry point. The trampoline makes sure that TempReg has been reloaded."<br>
self annotateBytecode: self Label.<br>
<br>
self Jump: retry.<br>
<br>
ok jmpTarget: self Label.<br>
^0!<br>
<br>
</blockquote></div><br></div>