<div dir="ltr">Hi Doug, Hi Tim, Hi All,<div><br></div><div> so yesterday I finally switched on the Raspberry Pi Doug gave me as an xmas present, built the Spur ARM Cog VM and ... we definitely have a working VM. I was able to update a Spur image from mid February all the way to tip and run tests. 3751 run, 3628 passes, 24 expected failures, 89 failures, 10 errors, 0 unexpected passes</div><div>Fun! So I want to revisit the literal load question.</div><div><br></div><div>Doug got me a Pi 1 B. cat /proc/cpuinfo reveals</div><div><div>processor<span class="Apple-tab-span" style="white-space:pre"> </span>: 0</div><div>model name<span class="Apple-tab-span" style="white-space:pre"> </span>: ARMv6-compatible processor rev 7 (v6l)</div><div>Features<span class="Apple-tab-span" style="white-space:pre"> </span>: swp half thumb fastmult vfp edsp java tls </div><div>CPU implementer<span class="Apple-tab-span" style="white-space:pre"> </span>: 0x41</div><div>CPU architecture: 7</div><div>CPU variant<span class="Apple-tab-span" style="white-space:pre"> </span>: 0x0</div><div>CPU part<span class="Apple-tab-span" style="white-space:pre"> </span>: 0xb76</div><div>CPU revision<span class="Apple-tab-span" style="white-space:pre"> </span>: 7</div><div><br></div><div>Hardware<span class="Apple-tab-span" style="white-space:pre"> </span>: BCM2708</div><div>Revision<span class="Apple-tab-span" style="white-space:pre"> </span>: 000e</div><div>Serial<span class="Apple-tab-span" style="white-space:pre"> </span>: 00000000fe7b08eb</div></div><div><br></div><div>And the <a href="http://www.keil.com/support/man/docs/armasm/armasm_dom1359731146222.htm">ARM Assembler User Guide</a> says (emphasis added)</div><div><div>4.4 Load immediate values using MOV and MVN</div><div>The MOV and MVN instructions can write a range of immediate values to a register.</div><div><br></div><div>In ARM state:</div><div>MOV can load any 8-bit immediate value, giving a range of 0x0-0xFF (0-255).</div><div>It can also rotate these values by any even number.</div><div>These values are also available as immediate operands in many data processing operations, without being loaded in a separate instruction.</div><div>MVN can load the bitwise complements of these values. The numerical values are -(n+1), where n is the value available in MOV.</div><div><b>In ARMv6T2 and later, MOV can load any 16-bit number, giving a range of 0x0-0xFFFF (0-65535).</b></div><div>The following table shows the range of 8-bit values that can be loaded in a single ARM MOV or MVN instruction (for data processing operations). The value to load must be a multiple of the value shown in the Step column.</div></div><div><br></div><div><br></div><div>So it looks to me that the right approach is to add an ARMv6 subclass to CogARMInstruction that uses the 16-bit literal load instructions and use that as our standard 32-bit ARM code generator. But I'm ignorant as to the processor versions used in the Raspberry Pi. Are all RPis ARMv6? What exactly is ARMv6T2? I'm guessing that T2 refers to Thunmb2, is that correct? And on the specific question can anyone think of a good reason /not/ to use the 16-bit literal load approach?</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, May 21, 2015 at 5:58 AM, Eliot Miranda <span dir="ltr"><<a href="mailto:eliot.miranda@gmail.com" target="_blank">eliot.miranda@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi Tim,<br>
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On May 21, 2015, at 12:47 AM, timfelgentreff <<a href="mailto:timfelgentreff@gmail.com">timfelgentreff@gmail.com</a>> wrote:<br>
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> Does the Pi1 work, too? Or are you using code specific to the newer cpu?<br>
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</span> TimR and I were talking about this yesterday. The current code generator targets ARMv5, and so works on Pi1.<br>
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Pi2 uses ARMv7 which, so TimR tells me, has a 16-bit literal load instruction, which means a 32-bit literal can be generated using two 32-bit instructions. ARMv5 either requires 4 32-bit instructions, or 1 32-bit instruction to access 1 32-bit literal out-of-line using PC-relative addressing. I'd like to know what the situation is for ARMv8 (the 64-bit ISA).<br>
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The temptation is to move to ARMv7 to get that more compact and faster literal generation. But it would mean either dropping Pi1 or two VMs. I'm not afraid of two VMs but it is more stuff, with all the headaches for newbies that entails. Another alternative might be to have the JIT test whether the system is v7 or not and generate the appropriate code, but that is problematic; the JIT will bloat and scanning machine code for object references will slow down.<br>
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Knowing what ARMv8 does for 64-bit literal synthesis would help me make up my mind. Whether the JIT should support out-of-line literal load is a somewhat significant issue; it's not something to write unless it's necessary.<br>
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Eliot (phone)<br>
<div class="HOEnZb"><div class="h5">><br>
> --<br>
> View this message in context: <a href="http://forum.world.st/ARM-Cog-progress-tp4827195p4827779.html" target="_blank">http://forum.world.st/ARM-Cog-progress-tp4827195p4827779.html</a><br>
> Sent from the Squeak VM mailing list archive at Nabble.com.<br>
</div></div></blockquote></div><br><br clear="all"><div><br></div>-- <br><div class="gmail_signature">best,<div>Eliot</div></div>
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