<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">2015-06-28 5:23 GMT+02:00 Eliot Miranda <span dir="ltr"><<a href="mailto:eliot.miranda@gmail.com" target="_blank">eliot.miranda@gmail.com</a>></span>:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"> <br><div dir="auto"><div>Hi Clément,</div><div><br></div><div> your code is quite correct. But the old code used two registers and I think that using two registers could be faster depending on processor micro architecture. So I wrote a version that used two registers if possible. Since I doubt it'll make any measurable difference (remote temps are rare and the cost of the sequence will be dominated by the reads) I reverted back to your original. But the support method might be useful. Sorry fir the noise.<br></div></div></blockquote><div><br></div><div>Ok I get it.</div><div><br></div><div>Anyway I am not pleased with my code because I'd like to rewrite it in a way where the register for the tempVector can be reused in-between instructions.</div><div><br></div><div>For example in this kind of code:</div><div><br></div><div>| t1 t2 t3 t4 |</div><div>[ t1 := t2 := t3 := t4 := 1.</div><div>self foo: t1 bar: t2 baz: t3 ] value</div><div><br></div><div>I think the tempVect can be stored once in the register and be reused directly for all the remote temp access. </div><div><br></div><div>But I want to implement it such as there is no specific case for tempVector but a generic case that works for inst vars, temp vectors and maybe more.</div><div><br></div><div>------</div><div><br></div><div>Unrelatedly, on ARM processor, I saw that you're not using r12. I would suggest to use it in register allocation. I have no ARM machine to try but the idea is:</div><div><br></div><div>CogRTLOpcodes class>>#initialize</div><div> ...</div><div>ExtraRegs := CArrayAccessor on: (Array new: 6).</div><div>...</div><div><br></div><div><div><div>CogAbstractInstruction>>#availableRegisterOrNilFor: liveRegsMask</div><div><span class="" style="white-space:pre"> </span>"Answer an unused abstract register in the liveRegMask."</div><div><span class="" style="white-space:pre"> </span><returnTypeC: #sqInt></div></div><div> 0 to: self numExtraRegs do: </div><div> [:i | </div><div><div><span class="" style="white-space:pre"> </span>(cogit register: (ExtraRegs at: i) isInMask: liveRegsMask) ifFalse:</div><div><span class="" style="white-space:pre"> </span>[^ (ExtraRegs at: i) ] ] .</div></div><div> (cogit register: Arg1Reg isInMask: liveRegsMask) ifFalse:</div><div><span class="" style="white-space:pre"> </span>[^Arg1Reg].</div><div><span class="" style="white-space:pre"> </span>(cogit register: Arg0Reg isInMask: liveRegsMask) ifFalse:</div><div><span class="" style="white-space:pre"> </span>[^Arg0Reg].</div><div><span class="" style="white-space:pre"> </span>(cogit register: SendNumArgsReg isInMask: liveRegsMask) ifFalse:</div><div><span class="" style="white-space:pre"> </span>[^SendNumArgsReg].</div><div><span class="" style="white-space:pre"> </span>(cogit register: ClassReg isInMask: liveRegsMask) ifFalse:</div><div><span class="" style="white-space:pre"> </span>[^ClassReg].</div><div><span class="" style="white-space:pre"> </span>(cogit register: ReceiverResultReg isInMask: liveRegsMask) ifFalse:</div><div><span class="" style="white-space:pre"> </span>[^ReceiverResultReg].</div><div><span class="" style="white-space:pre"> </span>^nil</div></div><div><br></div><div>CogARMCompiler>>#numExtraRegs</div><div> ^ 1</div><div><br></div><div>CogIA32Compiler>>#numExtraRegs</div><div> ^ 0</div><div><br></div><div>CogIA64Compiler>>#numExtraRegs</div><div> ^ 6</div><div><br></div><div>CogARMCompiler >>#concreteRegister: registerIndex<br></div><div>...</div><div><div><span class="" style="white-space:pre"> </span>[ExtraRegs at: 0]<span class="" style="white-space:pre"> </span>-> [R12].</div></div><div>...</div><div><br class="">There might be a few other place, like #abstractRegisterForConcreteRegister:, but I don't think it's a lot of complexity.<br></div><div><br></div><div>Then each instruction using register allocation (and there are quite some now) would use r12 prior to other regs. This can avoid some spills as the other regs are sometimes used for trampolines or by convention which is not the case of R12. In the non sista VM, it may make a difference to have 1 (or maybe 2) extra registers.</div><div><br></div><div>What do you think ?</div><div><br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"><div dir="auto"><div><br>Eliot (phone)</div><div><br>On Jun 27, 2015, at 3:25 PM, Clément Bera <<a href="mailto:bera.clement@gmail.com" target="_blank">bera.clement@gmail.com</a>> wrote:<br><br></div><blockquote type="cite"><div><span></span></div></blockquote><blockquote type="cite"><div><div dir="ltr">I am confused, what did you do in the two last commits ?<div><br></div><div>What is <span style="font-size:12.8000001907349px">example response ?</span></div><div><span style="font-size:12.8000001907349px"><br></span></div><div><span style="font-size:12.8000001907349px">Was my code correct ? I tried the simulator only and it worked fine. </span></div></div><div class="gmail_extra"><br><div class="gmail_quote">2015-06-27 21:44 GMT+02:00 <span dir="ltr"><<a href="mailto:commits@source.squeak.org" target="_blank">commits@source.squeak.org</a>></span>:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"><br>
Eliot Miranda uploaded a new version of VMMaker to project VM Maker:<br>
<a href="http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1391.mcz" rel="noreferrer" target="_blank">http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1391.mcz</a><br>
<br>
==================== Summary ====================<br>
<br>
Name: VMMaker.oscog-eem.1391<br>
Author: eem<br>
Time: 27 June 2015, 12:43:14.39 pm<br>
UUID: bdc64a36-203a-4f8f-b8e9-53ef7e41bfb9<br>
Ancestors: VMMaker.oscog-eem.1390<br>
<br>
Revert back to Clément's version of<br>
genPushRemoteTempLongBytecode now that<br>
example response has been committed.<br>
<br>
=============== Diff against VMMaker.oscog-eem.1390 ===============<br>
<br>
Item was changed:<br>
----- Method: StackToRegisterMappingCogit>>genPushRemoteTempLongBytecode (in category 'bytecode generators') -----<br>
genPushRemoteTempLongBytecode<br>
+ | newReg |<br>
- | newReg freeReg |<br>
newReg := self allocateRegNotConflictingWith: 0.<br>
+ self MoveMw: (self frameOffsetOfTemporary: byte2) r: FPReg R: newReg.<br>
- freeReg := self availableRegNotConflictingWith: (self registerMaskFor: newReg).<br>
- self MoveMw: (self frameOffsetOfTemporary: byte2) r: FPReg R: (freeReg ifNil: newReg).<br>
objectRepresentation<br>
genLoadSlot: byte1<br>
+ sourceReg: newReg<br>
- sourceReg: (freeReg ifNil: newReg)<br>
destReg: newReg.<br>
^self ssPushRegister: newReg!<br>
<br>
</blockquote></div><br></div>
</div></blockquote></div><br></blockquote></div><br></div></div>