<p dir="ltr">I don't think ARM or MIPS have an instruction that preserves the high bits in the destination register. How about using movzxb on ia32/x64?</p>
<div class="gmail_quote">On Nov 3, 2015 3:10 AM, "Eliot Miranda" <<a href="mailto:eliot.miranda@gmail.com">eliot.miranda@gmail.com</a>> wrote:<br type="attribution"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"> <br><div dir="auto"><div>Hi Ryan,</div><div><br>On Nov 2, 2015, at 8:51 PM, Ryan Macnak <<a href="mailto:rmacnak@gmail.com" target="_blank">rmacnak@gmail.com</a>> wrote:<br><br></div><blockquote type="cite"><div><span></span></div></blockquote><blockquote type="cite"><div><div dir="ltr">Does MoveAbR want zero extension or sign extension?</div></div></blockquote><div><br></div>If there is extension it must be zero extension. I *think* that on x86 assignment to %al, %bl et al on x86 leaves all other bits in the corresponding 32-bit register unchanged, so I stated in the comment for MoveMb:r:R: that if the code generator wants the higher bits zero it will explicitly zero the register before the byte load. I'll make the comment for MoveAb:R: explicit. To save the instruction I could add a backEnd query, eg backEnd byteLoadsZeroExtend.<span style="background-color:rgba(255,255,255,0)"><br><br>_,,,^..^,,,_ (phone)</span><div><br><blockquote type="cite"><div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Nov 2, 2015 at 6:17 PM, <span dir="ltr"><<a href="mailto:commits@source.squeak.org" target="_blank">commits@source.squeak.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><br>
Eliot Miranda uploaded a new version of VMMaker to project VM Maker:<br>
<a href="http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1504.mcz" rel="noreferrer" target="_blank">http://source.squeak.org/VMMaker/VMMaker.oscog-eem.1504.mcz</a><br>
<br>
==================== Summary ====================<br>
<br>
Name: VMMaker.oscog-eem.1504<br>
Author: eem<br>
Time: 2 November 2015, 10:16:22.592 pm<br>
UUID: 3c702143-ff40-4e38-a55e-065a3aec15ec<br>
Ancestors: VMMaker.oscog-EstebanLorenzano.1503<br>
<br>
Merge with VMMaker.oscog-EstebanLorenzano.1503:<br>
- simplify the addressIsInInstructions: macro.<br>
- express some concerns about ffiAddressOf:startingAt:size:<br>
<br>
x64 Cogit:<br>
Add support for MoveAb:R: & MoveR:Ab: on x64 & x86. Tim, would you mind adding support for ARM?<br>
The misuse of MoveMb:r:R:/MoveR:Mb:r: as a stand-in for MoveAb:R:/MoveR:Ab: only works on 32-bit platforms.<br>
<br>
Fix rip-relative addressing for MoveCwR/PushCw. Add some tests.<br>
<br>
Nuke the leaking breaks in genInnerPrimitiveNew[WithArg]:<br>
<br>
Execution now gets to the first jitted method that wants to create a closure.<br>
<br>
=============== Diff against VMMaker.oscog-EstebanLorenzano.1503 ===============<br>
<br>
Item was changed:<br>
----- Method: CogIA32Compiler>>computeMaximumSize (in category 'generate machine code') -----<br>
computeMaximumSize<br>
"Compute the maximum size for each opcode. This allows jump offsets to<br>
be determined, provided that all backward branches are long branches."<br>
"N.B. The ^N forms are to get around the bytecode compiler's long branch<br>
limits which are exceeded when each case jumps around the otherwise."<br>
opcode caseOf: {<br>
"Noops & Pseudo Ops"<br>
[Label] -> [^0].<br>
[AlignmentNops] -> [^(operands at: 0) - 1].<br>
[Fill16] -> [^2].<br>
[Fill32] -> [^4].<br>
[FillFromWord] -> [^4].<br>
[Nop] -> [^1].<br>
"Specific Control/Data Movement"<br>
[CDQ] -> [^1].<br>
[IDIVR] -> [^2].<br>
[IMULRR] -> [^3].<br>
[CPUID] -> [^2].<br>
[CMPXCHGAwR] -> [^7].<br>
[CMPXCHGMwrR] -> [^(self concreteRegister: (operands at: 1)) = ESP<br>
ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [5] ifFalse: [8]]<br>
ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]].<br>
[LFENCE] -> [^3].<br>
[MFENCE] -> [^3].<br>
[SFENCE] -> [^3].<br>
[LOCK] -> [^1].<br>
[XCHGAwR] -> [^6].<br>
[XCHGMwrR] -> [^(self concreteRegister: (operands at: 1)) = ESP<br>
ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]<br>
ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [3] ifFalse: [6]]].<br>
[XCHGRR] -> [^((self concreteRegister: (operands at: 0)) = EAX<br>
or: [(self concreteRegister: (operands at: 1)) = EAX])<br>
ifTrue: [1]<br>
ifFalse: [2]].<br>
"Control"<br>
[CallFull] -> [^5].<br>
[Call] -> [^5].<br>
[JumpR] -> [^2].<br>
[JumpFull] -> [self resolveJumpTarget. ^5].<br>
[JumpLong] -> [self resolveJumpTarget. ^5].<br>
[Jump] -> [self resolveJumpTarget. ^5].<br>
[JumpZero] -> [self resolveJumpTarget. ^6].<br>
[JumpNonZero] -> [self resolveJumpTarget. ^6].<br>
[JumpNegative] -> [self resolveJumpTarget. ^6].<br>
[JumpNonNegative] -> [self resolveJumpTarget. ^6].<br>
[JumpOverflow] -> [self resolveJumpTarget. ^6].<br>
[JumpNoOverflow] -> [self resolveJumpTarget. ^6].<br>
[JumpCarry] -> [self resolveJumpTarget. ^6].<br>
[JumpNoCarry] -> [self resolveJumpTarget. ^6].<br>
[JumpLess] -> [self resolveJumpTarget. ^6].<br>
[JumpGreaterOrEqual] -> [self resolveJumpTarget. ^6].<br>
[JumpGreater] -> [self resolveJumpTarget. ^6].<br>
[JumpLessOrEqual] -> [self resolveJumpTarget. ^6].<br>
[JumpBelow] -> [self resolveJumpTarget. ^6].<br>
[JumpAboveOrEqual] -> [self resolveJumpTarget. ^6].<br>
[JumpAbove] -> [self resolveJumpTarget. ^6].<br>
[JumpBelowOrEqual] -> [self resolveJumpTarget. ^6].<br>
[JumpLongZero] -> [self resolveJumpTarget. ^6].<br>
[JumpLongNonZero] -> [self resolveJumpTarget. ^6].<br>
[JumpFPEqual] -> [self resolveJumpTarget. ^6].<br>
[JumpFPNotEqual] -> [self resolveJumpTarget. ^6].<br>
[JumpFPLess] -> [self resolveJumpTarget. ^6].<br>
[JumpFPGreaterOrEqual] -> [self resolveJumpTarget. ^6].<br>
[JumpFPGreater] -> [self resolveJumpTarget. ^6].<br>
[JumpFPLessOrEqual] -> [self resolveJumpTarget. ^6].<br>
[JumpFPOrdered] -> [self resolveJumpTarget. ^6].<br>
[JumpFPUnordered] -> [self resolveJumpTarget. ^6].<br>
[RetN] -> [^(operands at: 0) = 0 ifTrue: [1] ifFalse: [3]].<br>
[Stop] -> [^1].<br>
<br>
"Arithmetic"<br>
[AddCqR] -> [^(self isQuick: (operands at: 0))<br>
ifTrue: [3]<br>
ifFalse: [(self concreteRegister: (operands at: 1)) = EAX<br>
ifTrue: [5]<br>
ifFalse: [6]]].<br>
[AndCqR] -> [^(self isQuick: (operands at: 0))<br>
ifTrue: [3]<br>
ifFalse: [(self concreteRegister: (operands at: 1)) = EAX<br>
ifTrue: [5]<br>
ifFalse: [6]]].<br>
[CmpCqR] -> [^(self isQuick: (operands at: 0))<br>
ifTrue: [3]<br>
ifFalse: [(self concreteRegister: (operands at: 1)) = EAX<br>
ifTrue: [5]<br>
ifFalse: [6]]].<br>
[OrCqR] -> [^(self isQuick: (operands at: 0))<br>
ifTrue: [3]<br>
ifFalse: [(self concreteRegister: (operands at: 1)) = EAX<br>
ifTrue: [5]<br>
ifFalse: [6]]].<br>
[SubCqR] -> [^(self isQuick: (operands at: 0))<br>
ifTrue: [3]<br>
ifFalse: [(self concreteRegister: (operands at: 1)) = EAX<br>
ifTrue: [5]<br>
ifFalse: [6]]].<br>
[TstCqR] -> [^((self isQuick: (operands at: 0)) and: [(self concreteRegister: (operands at: 1)) < 4])<br>
ifTrue: [3]<br>
ifFalse: [(self concreteRegister: (operands at: 1)) = EAX<br>
ifTrue: [5]<br>
ifFalse: [6]]].<br>
[AddCwR] -> [^(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]].<br>
[AndCwR] -> [^(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]].<br>
[CmpCwR] -> [^(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]].<br>
[OrCwR] -> [^(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]].<br>
[SubCwR] -> [^(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]].<br>
[XorCwR] -> [^(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]].<br>
[AddRR] -> [^2].<br>
[AndRR] -> [^2].<br>
[CmpRR] -> [^2].<br>
[OrRR] -> [^2].<br>
[XorRR] -> [^2].<br>
[SubRR] -> [^2].<br>
[NegateR] -> [^2].<br>
[LoadEffectiveAddressMwrR]<br>
-> [^((self isQuick: (operands at: 0))<br>
ifTrue: [3]<br>
ifFalse: [6])<br>
+ ((self concreteRegister: (operands at: 1)) = ESP<br>
ifTrue: [1]<br>
ifFalse: [0])].<br>
[LogicalShiftLeftCqR] -> [^(operands at: 0) = 1 ifTrue: [2] ifFalse: [3]].<br>
[LogicalShiftRightCqR] -> [^(operands at: 0) = 1 ifTrue: [2] ifFalse: [3]].<br>
[ArithmeticShiftRightCqR] -> [^(operands at: 0) = 1 ifTrue: [2] ifFalse: [3]].<br>
[LogicalShiftLeftRR] -> [^self computeShiftRRSize].<br>
[LogicalShiftRightRR] -> [^self computeShiftRRSize].<br>
[ArithmeticShiftRightRR] -> [^self computeShiftRRSize].<br>
[AddRdRd] -> [^4].<br>
[CmpRdRd] -> [^4].<br>
[SubRdRd] -> [^4].<br>
[MulRdRd] -> [^4].<br>
[DivRdRd] -> [^4].<br>
[SqrtRd] -> [^4].<br>
"Data Movement"<br>
[MoveCqR] -> [^(operands at: 0) = 0 ifTrue: [2] ifFalse: [5]].<br>
[MoveCwR] -> [^5].<br>
[MoveRR] -> [^2].<br>
[MoveRdRd] -> [^4].<br>
[MoveAwR] -> [^(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]].<br>
[MoveRAw] -> [^(self concreteRegister: (operands at: 0)) = EAX ifTrue: [5] ifFalse: [6]].<br>
+ [MoveAbR] -> [^(self concreteRegister: (operands at: 1)) = EAX ifTrue: [5] ifFalse: [6]].<br>
+ [MoveRAb] -> [^(self concreteRegister: (operands at: 0)) = EAX ifTrue: [5] ifFalse: [6]].<br>
[MoveRMwr] -> [^((self isQuick: (operands at: 1))<br>
ifTrue: [((operands at: 1) = 0<br>
and: [(self concreteRegister: (operands at: 2)) ~= EBP])<br>
ifTrue: [2]<br>
ifFalse: [3]]<br>
ifFalse: [6])<br>
+ ((self concreteRegister: (operands at: 2)) = ESP<br>
ifTrue: [1]<br>
ifFalse: [0])].<br>
[MoveRdM64r] -> [^((self isQuick: (operands at: 1))<br>
ifTrue: [5]<br>
ifFalse: [8])<br>
+ ((self concreteRegister: (operands at: 2)) = ESP<br>
ifTrue: [1]<br>
ifFalse: [0])].<br>
[MoveMbrR] -> [^(self concreteRegister: (operands at: 1)) = ESP<br>
ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [5] ifFalse: [8]]<br>
ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]].<br>
[MoveRMbr] -> [^(self concreteRegister: (operands at: 2)) = ESP<br>
ifTrue: [7]<br>
ifFalse: [(self isQuick: (operands at: 1)) ifTrue: [3] ifFalse: [6]]].<br>
[MoveM16rR] -> [^(self concreteRegister: (operands at: 1)) = ESP<br>
ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [5] ifFalse: [8]]<br>
ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]].<br>
[MoveM64rRd] -> [^((self isQuick: (operands at: 0))<br>
ifTrue: [5]<br>
ifFalse: [8])<br>
+ ((self concreteRegister: (operands at: 1)) = ESP<br>
ifTrue: [1]<br>
ifFalse: [0])].<br>
[MoveMwrR] -> [^((self isQuick: (operands at: 0))<br>
ifTrue: [((operands at: 0) = 0<br>
and: [(self concreteRegister: (operands at: 1)) ~= EBP])<br>
ifTrue: [2]<br>
ifFalse: [3]]<br>
ifFalse: [6])<br>
+ ((self concreteRegister: (operands at: 1)) = ESP<br>
ifTrue: [1]<br>
ifFalse: [0])].<br>
[MoveXbrRR] -> [self assert: (self concreteRegister: (operands at: 0)) ~= ESP.<br>
^(self concreteRegister: (operands at: 1)) = EBP<br>
ifTrue: [5]<br>
ifFalse: [4]].<br>
[MoveRXbrR] -> [self assert: (self concreteRegister: (operands at: 1)) ~= ESP.<br>
^((self concreteRegister: (operands at: 2)) = EBP<br>
ifTrue: [4]<br>
ifFalse: [3])<br>
+ ((self concreteRegister: (operands at: 0)) >= 4<br>
ifTrue: [2]<br>
ifFalse: [0])].<br>
[MoveXwrRR] -> [self assert: (self concreteRegister: (operands at: 0)) ~= ESP.<br>
^(self concreteRegister: (operands at: 1)) = EBP<br>
ifTrue: [4]<br>
ifFalse: [3]].<br>
[MoveRXwrR] -> [self assert: (self concreteRegister: (operands at: 1)) ~= ESP.<br>
^(self concreteRegister: (operands at: 2)) = EBP<br>
ifTrue: [4]<br>
ifFalse: [3]].<br>
[PopR] -> [^1].<br>
[PushR] -> [^1].<br>
[PushCq] -> [^(self isQuick: (operands at: 0)) ifTrue: [2] ifFalse: [5]].<br>
[PushCw] -> [^5].<br>
[PrefetchAw] -> [^self hasSSEInstructions ifTrue: [7] ifFalse: [0]].<br>
"Conversion"<br>
[ConvertRRd] -> [^4] }.<br>
^0 "to keep C compiler quiet"!<br>
<br>
Item was added:<br>
+ ----- Method: CogIA32Compiler>>concretizeMoveAbR (in category 'generate machine code') -----<br>
+ concretizeMoveAbR<br>
+ "Will get inlined into concretizeAt: switch."<br>
+ <inline: true><br>
+ | addressOperand reg |<br>
+ addressOperand := operands at: 0.<br>
+ (self isAnInstruction: (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *')) ifTrue:<br>
+ [addressOperand := (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *') address].<br>
+ reg := self concreteRegister: (operands at: 1).<br>
+ reg = EAX ifTrue:<br>
+ [machineCode<br>
+ at: 0 put: 16rA0;<br>
+ at: 1 put: (addressOperand bitAnd: 16rFF);<br>
+ at: 2 put: (addressOperand >> 8 bitAnd: 16rFF);<br>
+ at: 3 put: (addressOperand >> 16 bitAnd: 16rFF);<br>
+ at: 4 put: (addressOperand >> 24 bitAnd: 16rFF).<br>
+ ^machineCodeSize := 5].<br>
+ machineCode<br>
+ at: 0 put: 16r8A;<br>
+ at: 1 put: (self mod: ModRegInd RM: 5 RO: reg);<br>
+ at: 2 put: (addressOperand bitAnd: 16rFF);<br>
+ at: 3 put: (addressOperand >> 8 bitAnd: 16rFF);<br>
+ at: 4 put: (addressOperand >> 16 bitAnd: 16rFF);<br>
+ at: 5 put: (addressOperand >> 24 bitAnd: 16rFF).<br>
+ ^machineCodeSize := 6!<br>
<br>
Item was added:<br>
+ ----- Method: CogIA32Compiler>>concretizeMoveRAb (in category 'generate machine code') -----<br>
+ concretizeMoveRAb<br>
+ "Will get inlined into concretizeAt: switch."<br>
+ <inline: true><br>
+ | addressOperand reg |<br>
+ reg := self concreteRegister: (operands at: 0).<br>
+ addressOperand := operands at: 1.<br>
+ (self isAnInstruction: (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *')) ifTrue:<br>
+ [addressOperand := (cogit cCoerceSimple: addressOperand to: #'AbstractInstruction *') address].<br>
+ reg = EAX ifTrue:<br>
+ [machineCode<br>
+ at: 0 put: 16rA2;<br>
+ at: 1 put: (addressOperand bitAnd: 16rFF);<br>
+ at: 2 put: (addressOperand >> 8 bitAnd: 16rFF);<br>
+ at: 3 put: (addressOperand >> 16 bitAnd: 16rFF);<br>
+ at: 4 put: (addressOperand >> 24 bitAnd: 16rFF).<br>
+ ^machineCodeSize := 5].<br>
+ machineCode<br>
+ at: 0 put: 16r88;<br>
+ at: 1 put: (self mod: ModRegInd RM: 5 RO: reg);<br>
+ at: 2 put: (addressOperand bitAnd: 16rFF);<br>
+ at: 3 put: (addressOperand >> 8 bitAnd: 16rFF);<br>
+ at: 4 put: (addressOperand >> 16 bitAnd: 16rFF);<br>
+ at: 5 put: (addressOperand >> 24 bitAnd: 16rFF).<br>
+ ^machineCodeSize := 6!<br>
<br>
Item was changed:<br>
----- Method: CogIA32Compiler>>dispatchConcretize (in category 'generate machine code') -----<br>
dispatchConcretize<br>
"Attempt to generate concrete machine code for the instruction at address.<br>
This is the inner dispatch of concretizeAt: actualAddress which exists only<br>
to get around the branch size limits in the SqueakV3 (blue book derived)<br>
bytecode set."<br>
<returnTypeC: #void><br>
opcode caseOf: {<br>
"Noops & Pseudo Ops"<br>
[Label] -> [^self concretizeLabel].<br>
[AlignmentNops] -> [^self concretizeAlignmentNops].<br>
[Fill16] -> [^self concretizeFill16].<br>
[Fill32] -> [^self concretizeFill32].<br>
[FillFromWord] -> [^self concretizeFillFromWord].<br>
[Nop] -> [^self concretizeNop].<br>
"Specific Control/Data Movement"<br>
[CDQ] -> [^self concretizeCDQ].<br>
[IDIVR] -> [^self concretizeIDIVR].<br>
[IMULRR] -> [^self concretizeMulRR].<br>
[CPUID] -> [^self concretizeCPUID].<br>
[CMPXCHGAwR] -> [^self concretizeCMPXCHGAwR].<br>
[CMPXCHGMwrR] -> [^self concretizeCMPXCHGMwrR].<br>
[LFENCE] -> [^self concretizeFENCE: 5].<br>
[MFENCE] -> [^self concretizeFENCE: 6].<br>
[SFENCE] -> [^self concretizeFENCE: 7].<br>
[LOCK] -> [^self concretizeLOCK].<br>
[XCHGAwR] -> [^self concretizeXCHGAwR].<br>
[XCHGMwrR] -> [^self concretizeXCHGMwrR].<br>
[XCHGRR] -> [^self concretizeXCHGRR].<br>
"Control"<br>
[Call] -> [^self concretizeCall].<br>
[CallFull] -> [^self concretizeCall].<br>
[JumpR] -> [^self concretizeJumpR].<br>
[JumpFull] -> [^self concretizeJumpLong].<br>
[JumpLong] -> [^self concretizeJumpLong].<br>
[JumpLongZero] -> [^self concretizeConditionalJump: 16r4].<br>
[JumpLongNonZero] -> [^self concretizeConditionalJump: 16r5].<br>
[Jump] -> [^self concretizeJump].<br>
"Table B-1 IntelŽ 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture"<br>
[JumpZero] -> [^self concretizeConditionalJump: 16r4].<br>
[JumpNonZero] -> [^self concretizeConditionalJump: 16r5].<br>
[JumpNegative] -> [^self concretizeConditionalJump: 16r8].<br>
[JumpNonNegative] -> [^self concretizeConditionalJump: 16r9].<br>
[JumpOverflow] -> [^self concretizeConditionalJump: 16r0].<br>
[JumpNoOverflow] -> [^self concretizeConditionalJump: 16r1].<br>
[JumpCarry] -> [^self concretizeConditionalJump: 16r2].<br>
[JumpNoCarry] -> [^self concretizeConditionalJump: 16r3].<br>
[JumpLess] -> [^self concretizeConditionalJump: 16rC].<br>
[JumpGreaterOrEqual] -> [^self concretizeConditionalJump: 16rD].<br>
[JumpGreater] -> [^self concretizeConditionalJump: 16rF].<br>
[JumpLessOrEqual] -> [^self concretizeConditionalJump: 16rE].<br>
[JumpBelow] -> [^self concretizeConditionalJump: 16r2].<br>
[JumpAboveOrEqual] -> [^self concretizeConditionalJump: 16r3].<br>
[JumpAbove] -> [^self concretizeConditionalJump: 16r7].<br>
[JumpBelowOrEqual] -> [^self concretizeConditionalJump: 16r6].<br>
[JumpFPEqual] -> [^self concretizeConditionalJump: 16r4].<br>
[JumpFPNotEqual] -> [^self concretizeConditionalJump: 16r5].<br>
[JumpFPLess] -> [^self concretizeConditionalJump: 16r2].<br>
[JumpFPGreaterOrEqual] -> [^self concretizeConditionalJump: 16r3].<br>
[JumpFPGreater] -> [^self concretizeConditionalJump: 16r7].<br>
[JumpFPLessOrEqual] -> [^self concretizeConditionalJump: 16r6].<br>
[JumpFPOrdered] -> [^self concretizeConditionalJump: 16rB].<br>
[JumpFPUnordered] -> [^self concretizeConditionalJump: 16rA].<br>
[RetN] -> [^self concretizeRetN].<br>
[Stop] -> [^self concretizeStop].<br>
"Arithmetic"<br>
[AddCqR] -> [^self concretizeAddCqR].<br>
[AddCwR] -> [^self concretizeAddCwR].<br>
[AddRR] -> [^self concretizeAddRR].<br>
[AddRdRd] -> [^self concretizeSEE2OpRdRd: 16r58].<br>
[AndCqR] -> [^self concretizeAndCqR].<br>
[AndCwR] -> [^self concretizeAndCwR].<br>
[AndRR] -> [^self concretizeAndRR].<br>
[TstCqR] -> [^self concretizeTstCqR].<br>
[CmpCqR] -> [^self concretizeCmpCqR].<br>
[CmpCwR] -> [^self concretizeCmpCwR].<br>
[CmpRR] -> [^self concretizeCmpRR].<br>
[CmpRdRd] -> [^self concretizeCmpRdRd].<br>
[DivRdRd] -> [^self concretizeSEE2OpRdRd: 16r5E].<br>
[MulRdRd] -> [^self concretizeSEE2OpRdRd: 16r59].<br>
[OrCqR] -> [^self concretizeOrCqR].<br>
[OrCwR] -> [^self concretizeOrCwR].<br>
[OrRR] -> [^self concretizeOrRR].<br>
[SubCqR] -> [^self concretizeSubCqR].<br>
[SubCwR] -> [^self concretizeSubCwR].<br>
[SubRR] -> [^self concretizeSubRR].<br>
[SubRdRd] -> [^self concretizeSEE2OpRdRd: 16r5C].<br>
[SqrtRd] -> [^self concretizeSqrtRd].<br>
[XorCwR] -> [^self concretizeXorCwR].<br>
[XorRR] -> [^self concretizeXorRR].<br>
[NegateR] -> [^self concretizeNegateR].<br>
[LoadEffectiveAddressMwrR] -> [^self concretizeLoadEffectiveAddressMwrR].<br>
[ArithmeticShiftRightCqR] -> [^self concretizeArithmeticShiftRightCqR].<br>
[LogicalShiftRightCqR] -> [^self concretizeLogicalShiftRightCqR].<br>
[LogicalShiftLeftCqR] -> [^self concretizeLogicalShiftLeftCqR].<br>
[ArithmeticShiftRightRR] -> [^self concretizeArithmeticShiftRightRR].<br>
[LogicalShiftLeftRR] -> [^self concretizeLogicalShiftLeftRR].<br>
"Data Movement"<br>
[MoveCqR] -> [^self concretizeMoveCqR].<br>
[MoveCwR] -> [^self concretizeMoveCwR].<br>
[MoveRR] -> [^self concretizeMoveRR].<br>
[MoveAwR] -> [^self concretizeMoveAwR].<br>
[MoveRAw] -> [^self concretizeMoveRAw].<br>
+ [MoveAbR] -> [^self concretizeMoveAbR].<br>
+ [MoveRAb] -> [^self concretizeMoveRAb].<br>
[MoveMbrR] -> [^self concretizeMoveMbrR].<br>
[MoveRMbr] -> [^self concretizeMoveRMbr].<br>
[MoveM16rR] -> [^self concretizeMoveM16rR].<br>
[MoveM64rRd] -> [^self concretizeMoveM64rRd].<br>
[MoveMwrR] -> [^self concretizeMoveMwrR].<br>
[MoveXbrRR] -> [^self concretizeMoveXbrRR].<br>
[MoveRXbrR] -> [^self concretizeMoveRXbrR].<br>
[MoveXwrRR] -> [^self concretizeMoveXwrRR].<br>
[MoveRXwrR] -> [^self concretizeMoveRXwrR].<br>
[MoveRMwr] -> [^self concretizeMoveRMwr].<br>
[MoveRdM64r] -> [^self concretizeMoveRdM64r].<br>
[PopR] -> [^self concretizePopR].<br>
[PushR] -> [^self concretizePushR].<br>
[PushCq] -> [^self concretizePushCq].<br>
[PushCw] -> [^self concretizePushCw].<br>
[PrefetchAw] -> [^self concretizePrefetchAw].<br>
"Conversion"<br>
[ConvertRRd] -> [^self concretizeConvertRRd] }!<br>
<br>
Item was added:<br>
+ ----- Method: CogIA32CompilerTests>>testMoveAbR (in category 'tests') -----<br>
+ testMoveAbR<br>
+ "self new testMoveAbR"<br>
+ CogIA32CompilerForTests byteRegistersWithNamesDo:<br>
+ [:reg :regname|<br>
+ #(16r555555 16rAAAAAA) do:<br>
+ [:addr| | inst len |<br>
+ inst := self gen: MoveAbR operand: addr operand: reg.<br>
+ len := inst concretizeAt: 0.<br>
+ self processor<br>
+ disassembleInstructionAt: 0<br>
+ In: inst machineCode object<br>
+ into: [:str :sz| | plainJane herIntended |<br>
+ "Convert e.g. '00000000: movl %eax, 0x2(%eax) : 89 40 02' to 'movl %eax, 0x2(%eax)'"<br>
+ plainJane := self strip: str.<br>
+ herIntended := 'movb 0x', (addr hex allButFirst: 3), ', ', regname.<br>
+ self assert: (plainJane match: herIntended).<br>
+ self assert: len = sz]]]!<br>
<br>
Item was added:<br>
+ ----- Method: CogIA32CompilerTests>>testMoveRAb (in category 'tests') -----<br>
+ testMoveRAb<br>
+ "self new testMoveRAb"<br>
+ CogIA32CompilerForTests byteRegistersWithNamesDo:<br>
+ [:reg :regname|<br>
+ #(16r555555 16rAAAAAA) do:<br>
+ [:addr| | inst len |<br>
+ inst := self gen: MoveRAb operand: reg operand: addr.<br>
+ len := inst concretizeAt: 0.<br>
+ self processor<br>
+ disassembleInstructionAt: 0<br>
+ In: inst machineCode object<br>
+ into: [:str :sz| | plainJane herIntended |<br>
+ plainJane := self strip: str.<br>
+ herIntended := 'movb ', regname, ', 0x', (addr hex allButFirst: 3).<br>
+ self assert: (plainJane match: herIntended).<br>
+ self assert: len = sz]]]!<br>
<br>
Item was changed:<br>
----- Method: CogInLineLiteralsX64Compiler>>concretizeMoveCwR (in category 'generate machine code') -----<br>
concretizeMoveCwR<br>
"Will get inlined into concretizeAt: switch."<br>
<inline: true><br>
| value reg offset |<br>
value := operands at: 0.<br>
reg := self concreteRegister: (operands at: 1).<br>
(self isAnInstruction: (cogit cCoerceSimple: value to: #'AbstractInstruction *')) ifTrue:<br>
[value := (cogit cCoerceSimple: value to: #'AbstractInstruction *') address].<br>
(cogit addressIsInCurrentCompilation: value) ifTrue:<br>
[offset := value - (address + 7).<br>
machineCode<br>
at: 0 put: (self rexR: reg x: 0 b: 0);<br>
+ at: 1 put: 16r8D; "LoadEffectiveAddress"<br>
+ at: 2 put: (self mod: ModRegInd RM: 5 RO: reg);<br>
- at: 1 put: 16r8B;<br>
- at: 2 put: (self mod: ModReg RM: 5 RO: reg);<br>
at: 3 put: (offset bitAnd: 16rFF);<br>
at: 4 put: (offset >> 8 bitAnd: 16rFF);<br>
at: 5 put: (offset >> 16 bitAnd: 16rFF);<br>
at: 6 put: (offset >> 24 bitAnd: 16rFF).<br>
^machineCodeSize := 7].<br>
machineCode<br>
at: 0 put: (self rexR: reg x: 0 b: reg);<br>
at: 1 put: 16rB8 + (reg bitAnd: 7);<br>
at: 2 put: (value bitAnd: 16rFF);<br>
at: 3 put: (value >> 8 bitAnd: 16rFF);<br>
at: 4 put: (value >> 16 bitAnd: 16rFF);<br>
at: 5 put: (value >> 24 bitAnd: 16rFF);<br>
at: 6 put: (value >> 32 bitAnd: 16rFF);<br>
at: 7 put: (value >> 40 bitAnd: 16rFF);<br>
at: 8 put: (value >> 48 bitAnd: 16rFF);<br>
at: 9 put: (value >> 56 bitAnd: 16rFF);<br>
at: 10 put: 16r90. "Add a nop to disambiguate between MoveCwR/PushCwR and ArithCwR, which ends with a (self mod: ModReg RM: 0 RO: 0)"<br>
self assert: (self mod: ModReg RM: 0 RO: 0) > 16r90.<br>
^machineCodeSize := 11!<br>
<br>
Item was changed:<br>
----- Method: CogInLineLiteralsX64Compiler>>concretizePushCw (in category 'generate machine code') -----<br>
concretizePushCw<br>
"Will get inlined into concretizeAt: switch."<br>
<inline: true><br>
| value offset |<br>
value := operands at: 0.<br>
(self isAnInstruction: (cogit cCoerceSimple: value to: #'AbstractInstruction *')) ifTrue:<br>
[value := (cogit cCoerceSimple: value to: #'AbstractInstruction *') address].<br>
(cogit addressIsInCurrentCompilation: value) ifTrue:<br>
+ [offset := value - (address + 7).<br>
- [offset := value - (address + 6).<br>
machineCode<br>
+ at: 0 put: (self rexR: ConcreteRISCTempReg x: 0 b: 0);<br>
+ at: 1 put: 16r8D; "LoadEffectiveAddress"<br>
+ at: 2 put: (self mod: ModRegInd RM: 5 RO: ConcreteRISCTempReg);<br>
+ at: 3 put: (offset bitAnd: 16rFF);<br>
+ at: 4 put: (offset >> 8 bitAnd: 16rFF);<br>
+ at: 5 put: (offset >> 16 bitAnd: 16rFF);<br>
+ at: 6 put: (offset >> 24 bitAnd: 16rFF);<br>
+ at: 7 put: 16r41;<br>
+ at: 8 put: 16r48 + ConcreteRISCTempReg.<br>
+ ^machineCodeSize := 9].<br>
- at: 0 put: 16rFF;<br>
- at: 1 put: 16r35;<br>
- at: 2 put: (offset bitAnd: 16rFF);<br>
- at: 3 put: (offset >> 8 bitAnd: 16rFF);<br>
- at: 4 put: (offset >> 16 bitAnd: 16rFF);<br>
- at: 5 put: (offset >> 24 bitAnd: 16rFF).<br>
- ^machineCodeSize := 6].<br>
machineCode<br>
at: 0 put: (self rexR: ConcreteRISCTempReg x: 0 b: ConcreteRISCTempReg);<br>
at: 1 put: 16rB8 + (ConcreteRISCTempReg bitAnd: 7);<br>
at: 2 put: (value bitAnd: 16rFF);<br>
at: 3 put: (value >> 8 bitAnd: 16rFF);<br>
at: 4 put: (value >> 16 bitAnd: 16rFF);<br>
at: 5 put: (value >> 24 bitAnd: 16rFF);<br>
at: 6 put: (value >> 32 bitAnd: 16rFF);<br>
at: 7 put: (value >> 40 bitAnd: 16rFF);<br>
at: 8 put: (value >> 48 bitAnd: 16rFF);<br>
at: 9 put: (value >> 56 bitAnd: 16rFF);<br>
at: 10 put: 16r41;<br>
+ at: 11 put: 16r48 + ConcreteRISCTempReg. "The 48 will disambiguate between MoveCwR, PushCwR and ArithCwR, which ends with a (self mod: ModReg RM: 0 RO: 0)"<br>
- at: 11 put: 16r50 + (ConcreteRISCTempReg - 8). "The 50 will disambiguate between MoveCwR, PushCwR and ArithCwR, which ends with a (self mod: ModReg RM: 0 RO: 0)"<br>
self assert: ConcreteRISCTempReg >= 8.<br>
self assert: (self mod: ModReg RM: 0 RO: 0) > 16r57.<br>
^machineCodeSize := 12!<br>
<br>
Item was changed:<br>
----- Method: CogObjectRepresentationFor64BitSpur>>genInnerPrimitiveNew: (in category 'primitive generators') -----<br>
genInnerPrimitiveNew: retNoffset<br>
"Implement primitiveNew for convenient cases:<br>
- the receiver has a hash<br>
- the receiver is fixed size (excluding ephemerons to save instructions & miniscule time)<br>
- single word header/num slots < numSlotsMask<br>
- the result fits in eden (actually below scavengeThreshold)"<br>
<br>
| headerReg fillReg instSpecReg byteSizeReg<br>
jumpUnhashed jumpVariableOrEphemeron jumpNoSpace jumpTooBig jumpHasSlots<br>
fillLoop skip |<br>
<var: 'skip' type: #'AbstractInstruction *'><br>
<var: 'fillLoop' type: #'AbstractInstruction *'><br>
<var: 'jumpTooBig' type: #'AbstractInstruction *'><br>
<var: 'jumpHasSlots' type: #'AbstractInstruction *'><br>
<var: 'jumpNoSpace' type: #'AbstractInstruction *'><br>
<var: 'jumpUnhashed' type: #'AbstractInstruction *'><br>
<var: 'jumpVariableOrEphemeron' type: #'AbstractInstruction *'><br>
<br>
"header will contain classIndex/class's hash & format & numSlots/fixed size and finally fill value (nilObject)."<br>
- self break.<br>
headerReg := fillReg := SendNumArgsReg.<br>
"inst spec will hold class's instance specification, then byte size and finally end of new object."<br>
instSpecReg := byteSizeReg := ClassReg.<br>
<br>
"get freeStart as early as possible so as not to wait later..."<br>
cogit MoveAw: objectMemory freeStartAddress R: Arg1Reg.<br>
"get class's hash & fail if 0"<br>
self genGetHashFieldNonImmOf: ReceiverResultReg into: headerReg.<br>
jumpUnhashed := cogit JumpZero: 0.<br>
"get class's format inst var for both inst spec (format field) and num fixed fields"<br>
self genLoadSlot: InstanceSpecificationIndex sourceReg: ReceiverResultReg destReg: TempReg.<br>
self genConvertSmallIntegerToIntegerInReg: TempReg.<br>
cogit MoveR: TempReg R: instSpecReg.<br>
cogit LogicalShiftRightCq: objectMemory fixedFieldsFieldWidth R: TempReg.<br>
cogit AndCq: objectMemory formatMask R: TempReg.<br>
cogit AndCq: objectMemory fixedFieldsOfClassFormatMask R: instSpecReg.<br>
"fail if not fixed or if ephemeron (rare beasts so save the cycles)"<br>
cogit CmpCq: objectMemory nonIndexablePointerFormat R: TempReg.<br>
jumpVariableOrEphemeron := cogit JumpAbove: 0.<br>
cogit CmpCq: objectMemory numSlotsMask R: instSpecReg.<br>
jumpTooBig := cogit JumpAboveOrEqual: 0.<br>
"Add format to classIndex/format in header; the add in numSlots"<br>
cogit LogicalShiftLeftCq: objectMemory formatShift R: TempReg.<br>
cogit AddR: TempReg R: headerReg.<br>
cogit MoveR: instSpecReg R: TempReg.<br>
cogit LogicalShiftLeftCq: objectMemory numSlotsFullShift R: TempReg.<br>
cogit AddR: TempReg R: headerReg.<br>
"compute byte size; remember 0-sized objects still need 1 slot."<br>
cogit CmpCq: 0 R: byteSizeReg. "a.k.a. instSpecReg"<br>
jumpHasSlots := cogit JumpNonZero: 0.<br>
cogit MoveCq: objectMemory baseHeaderSize * 2 R: byteSizeReg.<br>
skip := cogit Jump: 0.<br>
"round up to allocationUnit"<br>
jumpHasSlots jmpTarget:<br>
(cogit AddCq: objectMemory baseHeaderSize / objectMemory wordSize R: byteSizeReg).<br>
cogit LogicalShiftLeftCq: objectMemory shiftForWord R: byteSizeReg.<br>
skip jmpTarget:<br>
"check if allocation fits (freeSize + byteSize < scavengeThreshold); scavengeThreshold is constant."<br>
(cogit AddR: Arg1Reg R: byteSizeReg).<br>
cogit CmpCq: objectMemory getScavengeThreshold R: byteSizeReg.<br>
jumpNoSpace := cogit JumpAboveOrEqual: 0.<br>
"write back new freeStart; get result. byteSizeReg holds new freeStart, the limit of the object"<br>
cogit MoveR: byteSizeReg Aw: objectMemory freeStartAddress.<br>
cogit MoveR: Arg1Reg R: ReceiverResultReg.<br>
"write header"<br>
cogit MoveR: headerReg Mw: 0 r: Arg1Reg.<br>
"now fill"<br>
cogit LoadEffectiveAddressMw: objectMemory baseHeaderSize r: ReceiverResultReg R: Arg1Reg.<br>
cogit MoveCq: objectMemory nilObject R: fillReg.<br>
fillLoop :=<br>
cogit MoveR: fillReg Mw: 0 r: Arg1Reg.<br>
cogit AddCq: 8 R: Arg1Reg.<br>
cogit CmpR: Arg1Reg R: byteSizeReg.<br>
cogit JumpAbove: fillLoop.<br>
cogit RetN: retNoffset.<br>
<br>
jumpUnhashed jmpTarget:<br>
(jumpVariableOrEphemeron jmpTarget:<br>
(jumpTooBig jmpTarget:<br>
(jumpNoSpace jmpTarget: cogit Label))).<br>
<br>
^0!<br>
<br>
Item was changed:<br>
----- Method: CogObjectRepresentationFor64BitSpur>>genInnerPrimitiveNewWithArg: (in category 'primitive generators') -----<br>
genInnerPrimitiveNewWithArg: retNoffset<br>
"Implement primitiveNewWithArg for convenient cases:<br>
- the receiver has a hash<br>
- the receiver is variable and not compiled method<br>
- single word header/num slots < numSlotsMask<br>
- the result fits in eden<br>
See superclass method for dynamic frequencies of formats.<br>
For the moment we implement only arrayFormat, firstByteFormat & firstLongFormat"<br>
<br>
| headerReg fillReg instSpecReg byteSizeReg maxSlots<br>
jumpArrayTooBig jumpByteTooBig jumpLongTooBig<br>
jumpArrayFormat jumpByteFormat jumpBytePrepDone jumpLongPrepDone<br>
jumpUnhashed jumpNElementsNonInt jumpFailCuzFixed jumpNoSpace jumpHasSlots fillLoop skip |<br>
<var: 'skip' type: #'AbstractInstruction *'><br>
<var: 'fillLoop' type: #'AbstractInstruction *'><br>
<var: 'jumpHasSlots' type: #'AbstractInstruction *'><br>
<var: 'jumpNoSpace' type: #'AbstractInstruction *'><br>
<var: 'jumpUnhashed' type: #'AbstractInstruction *'><br>
<var: 'jumpByteFormat' type: #'AbstractInstruction *'><br>
<var: 'jumpByteTooBig' type: #'AbstractInstruction *'><br>
<var: 'jumpLongTooBig' type: #'AbstractInstruction *'><br>
<var: 'jumpArrayFormat' type: #'AbstractInstruction *'><br>
<var: 'jumpArrayTooBig' type: #'AbstractInstruction *'><br>
<var: 'jumpFailCuzFixed' type: #'AbstractInstruction *'><br>
<var: 'jumpBytePrepDone' type: #'AbstractInstruction *'><br>
<var: 'jumpLongPrepDone' type: #'AbstractInstruction *'><br>
<var: 'jumpNElementsNonInt' type: #'AbstractInstruction *'><br>
<br>
"header will contain cl</blockquote></div></div></div></blockquote></div></div><br>...</blockquote></div>