Hardware June 2007

hardware@lists.squeakfoundation.org

4 participants
5 discussions

Re: [Box-Admins] Missing reply-to header from hardware@lists.squeakfoundation.org
by Klaus D. Witzel 11 Jun '07

11 Jun '07

On Mon, 11 Jun 2007 22:10:30 +0200, Marcus Denker wrote: > > On 11.06.2007, at 20:15, Ken Causey wrote: > >> I believe that's due to a configuration choice that Matthew made >> for the mailing list. >> > > The standard for new lists is that they have no reply-to-list, but > this can be easily > changes... I could do it, if needed/wanted. Yes please. And thank you. Cheers Klaus > Marcus > >> Ken >> >> On Mon, 2007-06-11 at 19:16 +0200, Klaus D. Witzel wrote: >>> Hi box admins, >>> >>> the recent posting from hardware(a)lists.squeakfoundation.org >>> arrived here >>> without reply-to header (all other lists from >>> lists.squeakfoundation.org >>> which I'm subscribed to seem to transmit that header). >>> >>> So when doing a reply, the original sender (the poster's email >>> address) is >>> only available :( >>> >>> Thanx in advance. >>> >>> Cheers >>> Klaus >>> >

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Missing reply-to header from hardware@lists.squeakfoundation.org
by Klaus D. Witzel 11 Jun '07

11 Jun '07

Hi box admins, the recent posting from hardware(a)lists.squeakfoundation.org arrived here without reply-to header (all other lists from lists.squeakfoundation.org which I'm subscribed to seem to transmit that header). So when doing a reply, the original sender (the poster's email address) is only available :( Thanx in advance. Cheers Klaus

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FPGA Pointers and Device Poll
by Travis Kay 11 Jun '07

11 Jun '07

Hello All, I've recently bought a Spartan 3E Starter Kit and I'm wondering what other devices people are using. I'm new to hardware design and any pointers to material would be appreciated. I've found a few online resources for soft cores and stack machines etc... However, I know this list is for squeak and I would like to do some research in this area. Regards, Travis

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Fwd: Re: JOP and tagged memory
by Klaus D. Witzel 09 Jun '07

09 Jun '07

This is another message from my archive; discussed JOP+tagged memory, with Jecel and Martin. Cheers Klaus P.S. some background on JOP: http://www.jopdesign.com/ has info the board(s) used and the tool chain. ------- Forwarded message ------- From: "Martin Schoeberl" To: "Klaus D. Witzel" Cc: "Jecel Assumpcao Jr" Subject: Re: JOP and tagged memory Date: Wed, 29 Nov 2006 10:16:03 +0100 Dear Klaus, > I've been impressed by your development of JOP, what an exceptional > piece of work! thanks :-) > Of course I have questions. I considered posting to > java-processor(a)yahoogroups.com but I have no Java question. Instead: You can also post them there. But you get probabaly only an answer from me there ;-) > - what is the alignment of memory access, I couldn't read that out of > your timing.pdf document and other downloaded material. Because of the > dense packing of Java constants, class and method bits, is it so that > memory access is byte aligned. Or did I just overlook the info > somewhere in your documentation. All element are 32-bit aligned. In JOP all addresses and data structures count in words. There is no such thing as bytes or short (internally). I think I did not document this implementation detail in the thesis. > - I'm interested in an architecture which (besides a bytecode > instruction set) supports tagged memory. That is, every 32 bit word in > RAM and FLASH memory has (at least) one extra bit. Do you think that > JOP architecture can support that and, if so, have suggestions how to > achieve that. That could be of great use with JOP (e.g. for garbage collection). I was thinking to use tagged words on the on-chip stack to get exact roots for the GC. However, up to now I think it makes things too complicted with the 32-bit main memory. As you want to do it for all memories it makes sense. There is only this little problem: 33-bit memories are no available ;-) > - alternately, if memory access is aligned (except for bytecode and > [binary] strings), I consider to tag 32 bit pointers, which because of > the alignment then would have at least one bit freed for tagging. You mean using the two lower bits in the pointer? Not in JOP as the pointer actually count in words (= no byte addressing). However, as we will not use 4G words (= 16 GB) main memory with JOP there are plenty of bits free in the upper part of the pointer. > - I'm confident that it is (relative) easy to implement an other > bytecode instruction set, without compromizing JOP architecture. Was > that already done, is there experience, are there pointers. The core pipeline and microcode ISA is design to map easy to Java bytecode. It's a stack machine. If you want to implement another instruction set on top of the it should be similar. Do you think about .NET? AFAIK no one has done this. Cheers, Martin

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Fwd: You FPGA guys rule !
by Klaus D. Witzel 09 Jun '07

09 Jun '07

This a message from my archive; discussed FPGA+OOP with Jecel and Martin. Cheers Klaus ------- Forwarded message ------- From: "Klaus D. Witzel" To: "Jecel Assumpcao Jr", "Martin Schoeberl" Subject: You FPGA guys rule ! Date: Wed, 07 Feb 2007 22:04:03 +0100 Hi Jecel, Martin, just in case that you've never seen a project that aims for 1000 CPUs/chip, see - http://www.google.com/search?q=David+Patterson+A+New+Agenda+for+Parallel+HW… Enjoy! Cheers Klaus

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Hardware June 2007