As I mentioned in my talk at the Squeak BOF (on October 21 at
Nashville), I have suspended the RISC42 effort to focus on a processor
optimized for Squeak. The idea of this SiliconSqueak is to be fully
compatible with software implementations of the VM and to be as compact
as possible to allow multiple cores per system.
Since this will be essentially a hardware implementation of the
Interpreter, it is not reasonable to expect the same results as you
would get with a sophisticated adaptive compilation system on the
RISC42. But it should be more than good enough and will run the software
people already have instead of forcing them to migrate to my own Neo
Smalltalk (though I was extremely pleased with how the design for that
turned out). The idea is to instead incrementally improve Squeak.
The reason for this change in direction is that I was contacted three
months ago by a group developing neat things in Squeak and they needed a
product like this. I had already studied the issues regarding Squeak
compatible hardware in the past few years
looking carefully at this one more time it seemed like a practical and
You might consider the Java processor JOP (http://www.jopdesign.com/) as
proof that this kind of thing can be done. And David Ungar and Sam
Adams' work on the tile64 (also presented at the BOF) as proof that
Squeak can run on a large number of cores.
I haven't started actual work on this project, yet. But there was an
interesting dicussion with Eliot Miranda about his planned bytecodes for
Cog since it would be a good idea to track that. Hopefully this will be
something that will be practical interest to more people than what I had
been doing before.