Cache and Squeak Performance

Tim Olson tim at jumpnet.com
Fri Feb 13 19:36:53 UTC 1998


>>>>> "JohnM" == Maloney  <johnm at wdi.disney.com> writes:
>
>    JohnM> ...I believe much of the speed improvement is due to the
>    JohnM> new "backside" cache design and faster memory bus.  ...the
>All of this reminds me of an article by Dave Thomas in a magazine like
>JOOP maybe eight years ago. In it he predicted that software systems
>built using relatively small and simple virtual machines would be more
>and more practical as the entire VM fit in cache along with enough of
>the application and data.
>
>Well the newer Pentiums this year will have what? Two megabytes of
>level two cache?
>
>What does the Apple Mac G3 have?

The PowerPC 750 processor supports up to 1MB of L2 cache (but it is 2-way 
set-associative!).  The more important fact is that the L1 cache size is 
32K Instruction + 32K data, 8-way set-associative, which goes a long way 
towards caching the (non-jitter) VM working set.



     -- tim





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