There's memory bandwidth and there's memory transaction
sqrmax at cvtci.com.ar
sqrmax at cvtci.com.ar
Tue Feb 16 03:04:14 UTC 1999
>> The 68K has much more registers than the intel processors.
>And much more general ones.
Yep. Like twice as more.
>> These last registers have limited arithmetic capabilities, especially
>> the ones ending in S (for segment).
>In fact the segment registers have no arithmetic capability at all. They
>are just there to hold the "segment" part of addresses, so they are
>essential for addressing and useless for anything else.
Oh, but there are some LEA tricks that can help you do arithmetic with
those registers I guess... something like (but with registers exchanged and never
tried this myself):
LEA EAX, [EAX*4 + EAX] "Mul EAX by 5 in few clock cycles]
Stuff like this is better described in Asmedit's help, available at
>Actually the 68K processors always had a release date somewhat behind
>that of the same-generation Intel processor, always had fewer bugs (if
You should see the pdfs available at Intel showing the bugs of each
revision of processors. The list doesn't contain a few, it's much more than that!!!
>However, 68Ks didn't run DOS, so Motorola lost that race, and sometime
>after the 68030 they decided to leave the field to Intel and didn't tune
>the clock speed to the levels that Intel uses today.
I'm really sorry about this... I liked the 68K more than the 8088.
>> (like asynchronous IO for instance, why do you think intel machines
>> need FIFOs everywhere?).
>Hmm... that's a feature that I didn't see in my 68K specs. What do you
>mean with this?
>From where I read it, an text file from the amiga describing the 68K, it
meant that the cpu could initiate port accesses without having to wait until
completion, and so could go on executing stuff. I now think it has to do with
the amiga's chipset that controlled 25 dma channels. And PCs have 8... now all
this causes the motherboards to have FIFOs everywhere because the bus is
heavily used and/or the cpu will be flushing caches and losing thousands of
cycles resetting itself... from Asmedit's clock cycle chart, flushing caches in a
pentium processor needs 2000+ cycles, and context changes, mode changes and
so on are described as performance killers. And so it can't pay much
attention to IRQs and so data gets lost in the middle.
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