Optimizing Squeak

Tim Olson tim at jumpnet.com
Wed Feb 24 05:10:48 UTC 1999

Greg wrote:

     [good summary of BTAC & BTIC operation on bytecode dispatch]

>The BTIC used in the PPC 750 has a different purpose.  By caching the
>branch target instructions, these instructions can be decoded on the
>cycle following the decode of a branch instruction rather than two
>cycles afterwards.  However, it doesn't help predict addresses of
>indirect branches, so you always get a branch misprediction on any
>indirect branch.  

You are correct that the BTIC on the PPC 750 doesn't help predict the 
address for indirect branches.  However, in PowerPC, indirect branches 
are handled by moving the address to either the link or count register, 
then branching indirect on one of those.  If the move to the link or 
count register is performed sufficiently ahead of the indirect branch on 
the PPC 750 (say, in threaded code where the dispatch of the next 
instruction is handled by the tail end of the previous instruction), then 
no stall will occur, as there will be no prediction (the address is known 
when the branch is seen).

>I believe BHTs came before BTACs or BTICs...

The first BTIC I'm aware of is on the AMD 29K (ca 1987), while BHTs came 
to microprocessors later.

     -- tim

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