Hi,
   The new CASSIOPEIA E-100 uses a NEC VR4121 (131MHz) according to
Casio. Poking around on www.necel.com the VR4121 has a 16 kbyte
instruction and 8kbyte data cache with the MIPS III instruction set. 
Both the E-10 and E11 use the NEC VR4111, no speed specified.  Nec
Electronics lists a 70 and 90 mhz ones, both also with 16k I and 8k D
caches.

  According to the Product Flier for the VR4121, at 168mhz it runs at
224 Dhrystone MIPS.   So, at 131 mhz it should run at a linearly
extrapolated 174 Dhrystone MIPS (what ever those really are).  The
E-10/E-11, if we assume the 90 mhz ones, run at 115 Dhrystone MIPS.

  Contuining the bold extrapolation we get that 26 benchFib should run
in about 40 secs or so on a E-100.

  Poking at www.hitachi.com it looks like, a bit hard to tell exactly,
that the S3 used in the Win CE systems uses an 8 K unified I&D cache.

  You know, if Squeak is really slow I wonder if it's not a compiler
problem.  RICS chips really really like smart compilers :-)


  Cheers

bruce

johnm at wdi.disney.com wrote:

> bus bandwidth. Finally, these machines don't have L2
> caches (far too much of a power drain) and they may
> have insufficient on-chip caches to support Squeak.
> (Does anyone know what size caches the Hitachi SH3
> or MIPS 4000 chips have?)

> ohshima at is.titech.ac.jp wrote:

> >   When I took a look at Squeak 2.2 for WinCE on Casio E-11, 'WarpBlt
> > test3' ran pretty fast, but the performance of benchFib was
> > quite bad. (about 60 seconds for '26 benchFib'.)
> > 


==
Bruce O'Neel - beoneel at acm.org http://homepage.iprolink.ch/~bioneel
The corporate culture is concerned less with Occam's razor than his
aftershave lotion. -- R. L. Peskin <peskin at caip.rutgers.edu>
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