Squeak on FPGA custom CPUs
Jecel Assumpcao Jr
jecel at mail.merlintec.com
Fri Sep 8 20:16:54 UTC 2000
On Fri, 08 Sep 2000, Mike Rutenberg wrote:
> Any more you can say about your FPGA cpu Squeak VM?
Yes, even though it is a commercial project it is totally open. The
only reason I can't point you to a web page with all the little details
about it is that I haven't written them yet.
The architecture is called Tachyon and I have designed it to run the
Self VM (though I reduced the number of bytecodes from 8 to 4 since I
don't like to deal with large instruction sets ;-)
It is a combination of hardware and software (adaptive compilation,
what Transmeta calls "code morphing", translates the bytecodes to the
internal instruction format). Changing this software would allow you to
run Squeak or Java bytecodes, so this part would be changeable even if
I wasn't using an FPGA.
Running at 100 MHz, the FPGA fetches one 64 word in each clock cycle
from its "microcode cache" (combined with the data cache for a total
for 960KB). If there is a cache hit, then the word contains 4 sixteen
bit MOVE instructions (http://ce-serv.et.tudelft.nl/MOVE/), one for
each of the 4 internal busses. If there is a cache miss, then the
software must fetch the bytecodes and either interpret them directly or
translate them into MOVEs and place them in the cache so they can be
found the next time.
This microcode cache includes hardware support for polymorphic inline
caches (PICs) and "customization", the two main technologies that make
Self so fast.
> You are thinking of dynamically reprogramming it? Jitter VI :-) ?
Yes, I want to transform the most critical objects into hardware. This
will take a while to develop, of course. This could be done statically:
Slang --> C --> binary
Slang2 --> VHDL --> netlist --> bitstream
I would like something that was more dynamic than this, but it would
already be rather neat.
> There is an interesting small CPU core at http://www.fpgacpu.org (a 16
> bit MIPs architecture subset with 32 bit version in progress I believe).
> Two features may be of particular interest -- it implements a tightly
> designed system on a chip, with buses and IO, and leave lots of FPGA
> area free for other things (Squeak hardware!). Jan's focus was to
> design a well engineered, clearly explained CPU. There are couple of
> good and detailed articles on the web site. (When the 32 bit version is
> done, we have been thinking of getting up a Squeak VM on it).
I have seen this, but my design is much simpler (not counting any
functional units that I stuff in my FPGA that he doesn't have). His
great advantage is not requiring any software support (just patch some
MIPS compiler and OS) while mine is comparable to the Transmeta and IBM
It is much easier to port Squeak to the xr16, but more worthwhile
making it run on the Tachyon...
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