>Err, does this mean G3+ _only_ or not? I'm not hurt by this (Newer G4
>card - sweet!) but others may be, so clarification could be good.



>  > The readme is below.
>(snip)
>  >(k) Compiled for 750(G3) processor versus 603
>


The difference between a G3 and 603 compile on CW 5.3 seems to be how 
instructions are sequenced. For a 603 it might do

pseudo code

loadregister 1,0,2  load register 1 from 2
storeregister 1,0,3 store register 1 into 3
loadregister 4,0,5  load register 4 from 5

But if you compile for G3 then it changes it to

loadregister 1,0,2  load register 1 from 2
loadregister 4,0,5  load register 4 from 5
storeregister 1,0,3 store register 1 into 3

Since the G3 may do both loads of register 1 and 4 at the same time, 
versus stalling on the load/store register 1 sequence. I'm not sure 
why the 603 optimizer is so stupid...

Note that the G3 might reorder the instructions on the fly too (I 
think) RISC base CPUS are rather complex now...



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John M. McIntosh <johnmci at smalltalkconsulting.com> 1-800-477-2659
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