Scott A Crosby <crosby at qwes.math.cmu.edu> is widely believed to have written:


> Nope. Most cachelines are 16 bytes.
I doubt it. ARM uses a variety of cache line sizes ranging from 0 to 256
bytes. I think PPC uses 32 bytes. Sparc uses a variety depending on step
level (and just to add fun, the line range spec in the the flush
instruction varies; some levels use a closed interval, some a half-open
interval. Imagine the amusement derived from debugging a code generator
when SUN forgets to tell you this ).

tim

-- 
Tim Rowledge, tim at sumeru.stanford.edu, http://sumeru.stanford.edu/tim
Useful random insult:- All booster, no payload.