a tale of 4 cpus (was: CPU running smalltalk bytecode)
Tim Rowledge
tim at sumeru.stanford.edu
Mon Feb 11 22:41:48 UTC 2002
Jecel Assumpcao Jr <jecel at merlintec.com> is claimed by the authorities to have written:
> > However as I've said again and again (redundantly even), it's
> > bandwidth, bandwidth and bandwidth.
>
> Very true, but the only real solution is to give up the Von Neumann
> architecture entirely. So I am working on a fourth design which has
> message passing at the transistor level. Would 4.8e+16 bytes per second
> make you happy? This would be for a 1 million "cell" chip implemented
> in 0.18 micron technology. This architecture can't be implemented in
> FPGAs, unfortunately. I don't have a name for this one yet...
Well I suppose we could live with it...is that burst or steady flow
bandwidth? Costs for cache misses, branches etc? As for a name - how
about FHB? As in F*%%$%ng High Bandwidth :-)
tim
--
Tim Rowledge, tim at sumeru.stanford.edu, http://sumeru.stanford.edu/tim
Useful random insult:- Barney's his hero.
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