"Andreas Raab" <andreas.raab at gmx.de> wrote:

	[PowerPC 750 architecture stuff snipped]

| Very interesting - do you have a URL handy for this? I'd like to read
up on
| it.

I believe it is covered in the user's manual, which can be downloaded
from:

<http://www-3.ibm.com/chips/techlib/techlib.nsf/techdocs/852569B20050FF7
785256996006C28E2>
 
| > The 750 does have a 64-entry BTIC (Branch Target Instruction 
| > Cache), so it will see some benefit from the "goto indirect label"
| > feature of GCC.
| 
| Which makes me wonder if the BTIC is actually large enough to cover
the
| whole dispatch of my benchmark (only 20 bytecodes are involved) ...
perhaps
| we need to increase the number of bytecodes to actually see an effect
(it
| would certainly explain why John got the same measures).

The BTIC operates much like a BTAC, except that it holds the first two
target instructions, rather than the target address.  Like the BTAC, it
only associates one branch target with each branch location, so an
individual branch which alternates between multiple different targets
(like your misPredicted method does) will not see any benefit from it. 
So I suspect that you are right about John's timings being done on a VM
without the GCC branch indirect to label feature.

	-- Tim Olson