Richard,

	The NIOS is a synthesizable IP core for Altera FPGAs
i.e. It is simply a CPU that can be implemented on an FPGA.
There is no "NIOS chip" that is a hardwired CPU plus FPGA,
although there are a number of chips that fit this description.
The NIOS can be implemented on any sufficiently large Altera
FPGA.

Atmel has a device they call "FPSLIC" (Field Programmable
System Level Integrated Circuit) That includes a 20 MIPS AVR
RISC, 36K bytes of SRAM and up to 40K gates of programmable logic.

Xilinx has the Virtex II Pro FPGA which includes a 400 MHz
IBM PowerPC up to 10 Mbits of embedded block RAM, and a *lot*
of programmable logic resources.  These are pretty expensive
though.

				-Dean


> -----Original Message-----
> From: Richard A. O'Keefe [mailto:ok at cs.otago.ac.nz]
> Sent: Thursday, March 20, 2003 8:39 PM
> To: squeak-dev at lists.squeakfoundation.org
> Subject: Re: oo hardware (was: Why so few garage processors?)
> 
> 
> Alan wrote:
> 	...
> 	So I would look at one of the 
> 	modern processes that allows CPU and memory logic to be 
> on the same 
> 	die and try to make what is essentially an entire 
> machine on that die 
> 	(especially with regard to how processing, memories and 
> switching 
> 	relate).
> 
> Has anyone looked at the NIOS processor?  If I've understood 
> correctly,
> it's a C-friendly RISC +plus+ on-chip FPGA, so you can have 
> conventional
> code AND a rapidly-tweakable home-brew.
> 
>