On Thu, Jan 22, 2009 at 12:53 PM, David Farber <dfarber at numenor.com> wrote:

> Eliot - I know you've already moved past this problem, but in the future,
> gcc -S foo.c will create foo.s with the assembly generated by gcc.
>

Um, I know :)  Trouble is gcc also optimizes so it may not always generate
the code you expect.  For example,

issignedshift(v) { return (v >> 1) < 0 ? 1 : 0; }

will, with -O4, generate

       movl 4(%esp), %eax
       sarl $31,%eax
       ret

because it works out this is the quickest way to generate a 1 if v is
negative and doesn't generate a compare at all.

BTW, I've been abusing gcc's -S output for a long time.  Back in the 80's I
used to generate direct-threaded-code VMs using gcc where I would edit the
-S output with sed to produce the opcodes for the threaded code machine
stripped of the prolog and epilog gcc would produce.  I've also produced
JIT-compiled BitBlt by similar means with a number of different compilers.
 -S has been my friend for many years.

Cheers!
Eliot



> David
>
> On Jan 21, 2009, at 2:08 PM, Eliot Miranda wrote:
>
> Hi Martin,  can you send me the assembly?  Or show me the opcodes? When I
> try this it doesn't work.  So I must be doing something differently.
> and Hi!  Robert Hirschfeld mentioned you when he and I met last week.
>
> On Wed, Jan 21, 2009 at 11:06 AM, Martin Beck <
> martin.beck at hpi.uni-potsdam.de> wrote:
>
>> Hi Eliot,
>>
>> Eliot Miranda wrote:
>> > Hi All,
>> >     anyone know the x86/IA32 really well?  If so, read on.  Otherwise
>> save
>> > yourself the yawn.
>> >
>> [...]
>> > (my emphasis added).  But neither the Bochs simulator nor my Intel Core
>> Duo
>> > set the flags when doing sarl $1, %eax when %eax contains -1.  Have I
>> > misread, or is the manual wrong?
>> >
>> I cannot confirm this. Using this simple C-Program:
>>
>> int calc(int i) {
>>  return i >> 1;
>> }
>>
>> int main() {
>>  printf("%i\n", calc(-1));
>> }
>>
>> my GCC 4.3.2 generates a sarl %eax instruction as the assembler output
>> shows. Debugging it with Kdbg shows a change of the flags after the
>> instruction. In fact, CF and SF are set as (more or less) expected. I
>> also have a Intel Core 2 Duo.
>>
>> Regards,
>> Martin
>>
>>
>
>
>
>
>
>
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