Tony Garnock-Jones wrote:
> That was indeed very interesting!

Thanks! Unfortunately, my style of slides are not very useful without my
narration.

> Is your PhD dissertation available anywhere? I tried googling for it,
> but couldn't find anything.

The May 2015 version of the text is missing a bunch of chapters, but the
appendices have details about the processor's instruction set:

http://www.merlintec.com/download/jecel_phd_deposited.pdf

I made some changes to the project in October 2015 and updated the text,
but I still haven't finished it and put it online yet.

For those interested in Smalltalk hardware but who would prefer a quick
summary, the main idea is that in Von Neumann computers if you have
enough resources for the processor then the performance is limited by
the memory bandwidth. SiliconSqueak uses four different caches and a few
DMA style "stream units" to both increase the local memory bandwidth and
also to separate the different kinds of memory accesses so the SDRAM
controller can do a better job.

Another idea is that the Squeak Virtual Machine has three parts: the
bytecode interpreter, the object memory and the primitives/plugins. If
you could somehow execute bytecodes really fast, then you wouldn't need
the first part and you could execute the Slang version of the second and
third parts (just like you do in the simulator).

One interesting detail is how SiliconSqueak uses the code cache to
implement PICs (Polymorphic Inline Caches) with constant access times
instead of the linear times that Cog and such VMs use on normal
processors.

-- Jecel